First-Out (FIFO) memories w/ bus matching capabilities
• 1K × 36 × 2 (CY7C43644AV)
• 4K × 36 × 2 (CY7C43664AV)
• 16K × 36 × 2 (CY7C43684AV)
• 0.25-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5-ns Read/Write
cycle times)
• Low power
— I
CC
= 60 mA
— I
SB
= 10 mA
Table 1.
• Fully asynchronous and simultaneous Read and Write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT user selectable mode
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
MBF1
CLKA
CSA
W/RA
ENA
MBA
RT2
1K/4K/16K
× 36
Dual Ported
Memory
(FIFO 1)
Bus Matching
Port A
Control
Logic
Input
Register
Mail1
Register
CLKB
CSB
W/RB
ENB
MBB
RTI
BM
SIZE
Register
MRS1
PRS1
FIFO1,
Mail1
Reset
Logic
Write
Pointer
Read
Pointer
FFA/IRA
AFA
Status
Flag Logic
Output
Port B
Control
Logic
EFB/ORB
AEB
SPM
FS0/SD
FS1/SEN
A
0–35
EFA/ORA
AEA
36
Programmable
Flag Offset
Registers
Timing
Mode
36
B
0–35
BE/FWFT
Status
Flag Logic
Write
Pointer
Read
Pointer
FFB/IRB
AFB
1K/4K/16K
× 36
Dual Ported
Memory
(FIFO 2)
Mail2
Register
MBF2
Cypress Semiconductor Corporation
Document #: 38-06025 Rev. *C
Output
Register
•
3901 North First Street
•
San Jose
Input
Register
FIFO1,
Mail1
Reset
Logic
MRS2
PRS2
•
CA 95134 • 408-943-2600
Revised December 26, 2002
CY7C43644AV
CY7C43664AV
CY7C43684AV
Table 1.
Pin Configuration
[1]
TQFP
Top View
CSA
FFA/IRA
EFA/ORA
PRS1
V
CC
AFA
AEA
MBF2
MBA
MRS1
FS0/SD
NC
GND
FS1/SEN
MRS2
MBB
EFB/ORB
FFB/IRB
GND
CSB
W/RB
ENB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
W/RA
ENA
CLKA
GND
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
BE/FWFT
GND
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
RT2
A
12
GND
A
11
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
MBF1
V
CC
AEB
AFB
CY7C43644AV
CY7C43664AV
CY7C43684AV
CLKB
PRS2
V
CC
B
35
B
34
B
33
B
32
GND
NC
B
31
B
30
B
29
B
28
B
27
B
26
RT1
B
25
B
24
BM
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
SIZE
V
CC
B
15
B
14
B
13
B
12
GND
B
11
B
10
A
9
A
8
A
7
A
6
GND
A
5
A
4
A
3
SPM
V
CC
A
2
A
1
A
0
GND
B
0
B
1
B
2
B
3
B
4
B
5
Note:
1. Pin-compatible to IDT7236X4 family.
Document #: 38-06025 Rev. *C
GND
B
6
V
CC
B
7
B
8
B
9
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Page 2 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
Functional Description
The CY7C436X4AV is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous FIFO memory which
supports clock frequencies up to 133 MHz and has Read
access times as fast as 6 ns. Two independent 1K/4K/16K ×
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions. FIFO data on Port B can be input and
output in 36-bit, 18-bit, or 9-bit formats with a choice of Big or
Little Endian configurations.
The CY7C436X4AV is a synchronous (clocked) FIFO,
meaning each port employs a synchronous interface. All data
transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for each
port are independent of one another and can be asynchronous
or coincident. The enables for each port are arranged to
provide a simple bidirectional interface between micropro-
cessors and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436X4AV: Master
Reset and Partial Reset. Master Reset initializes the Read and
Write pointers to the first location of the memory array,
configures the FIFO for Big or Little Endian byte arrangement
and selects serial flag programming, parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. Each FIFO has its own independent
Master Reset pin, MRS1 and MRS2.
Partial Reset also sets the Read and Write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
partial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. Each FIFO has its own,
independent Partial Reset pin, PRS1 and PRS2.
The CY7C436X4AV have two modes of operation: In the CY
Standard mode, the first word written to an empty FIFO is
deposited into the memory array. A Read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through mode (FWFT), the
first long-word (36-bit wide) written to an empty FIFO appears
automatically on the outputs, no Read operation required
(nevertheless, accessing subsequent words does necessitate
a formal Read request). The state of the BE/FWFT pin during
FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready flag (EFA/
ORA and EFB/ORB) and a combined Full/Input Ready flag
(FFA/IRA and FFB/IRB). The EF and FF functions are selected
in the CY Standard mode. EF indicates whether the memory
is empty and FF indicates whether the FIFO memory is full.
The IR and OR functions are selected in the First-Word Fall-
Through mode. IR indicates whether or not the FIFO has
available memory locations. OR shows whether the FIFO has
data available for reading or not. It marks the presence of valid
data on the outputs.
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB are asserted when a selected number of words
written to FIFO memory achieve a predetermined “almost
empty state.” AFA and AFB are asserted when a selected
number of words written to the memory achieve a predeter-
mined “almost full state.”
[2]
IRA, IRB, AFA, and AFB are synchronized to the port clock that
writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AEB, AFA, and AFB are loaded
in parallel using Port A or in serial via the SD input. Three
default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AFA and AFB threshold can be set at 8, 16, or
64 locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. A Retransmit feature is available on these devices.
The CY7C436X4AV FIFOs are characterized for operation
from 0°C to 70°C commercial, and from –40°C to 85°C indus-
trial. Input ESD protection is greater than 2001V, and latch-up
is prevented by the use of guard rings.
Selection Guide
CY7C43644/64/84AV
–7
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-Up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply
Current (I
CC1
)
Commercial
Industrial
133
6
7.5
3
0
6
60
CY7C43644/64/84AV
–10
100
8
10
4
0
8
60
CY7C43644/64/84AV
–15
66.7
10
15
5
0
10
60
60
Unit
MHz
ns
ns
ns
ns
ns
mA
Note:
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to two clock cycles for flag deassertion, but the flag will always
be asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to Cypress’s
application note entitled “Designing with CY7C436xx Synchronous FIFOs” for more details on flag uncertainties.
Document #: 38-06025 Rev. *C
Page 3 of 37
CY7C43644AV
CY7C43664AV
CY7C43684AV
CY7C43644AV
Density
Package
1K × 36 × 2
128 TQFP
CY7C43664AV
4K × 36 × 2
128 TQFP
CY7C43684AV
16K × 36 × 2
128 TQFP
Pin Definitions
Signal Name
A
0–35
AEA
Description
Port A Data
Port A Almost
Empty Flag
Port B Almost
Empty Flag
Port A Almost
Full Flag
Port B Almost
Full Flag
Port B Data
Big Endian/
First-Word Fall-
Through Select
I/O
O
Function
Programmable Almost Empty flag synchronized to CLKA.
It is LOW when the
number of words in FIFO2 is less than or equal to the value in the Almost Empty A
offset register, X2.
[2]
Programmable Almost Empty flag synchronized to CLKB.
It is LOW when the
number of words in FIFO1 is less than or equal to the value in the Almost Empty B
offset register, X1.
[2]
Programmable Almost Full flag synchronized to CLKA (MHz).
It is LOW when the
number of empty locations in FIFO1 is less than or equal to the value in the Almost Full
A offset register, Y1.
[2]
Programmable Almost Full flag synchronized to CLKB.
It is LOW when the number
of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.
[2]
This is a dual-purpose pin.
During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word
on Port A is transferred to Port B first for A-to-B data flow. For data flowing from port B
to Port A, the first word/byte written to Port B will come out as the most significant word/
byte on port A. On the other hand, a LOW on BE will select Little Endian operation. In
this case, the least significant byte or word on Port A is transferred to Port B first for A-
to-B data flow. Similarly, the first word/byte written into port B will come out as the least
significant word/byte on Port A for B-to-A data flow. After Master Reset, this pin selects
the timing mode. A HIGH on BE/FWFT selects CY Standard mode, a LOW selects
First-Word Fall-Through mode. Once the timing mode has been selected, the level on
this pin must be static throughout device operation.
A HIGH on this pin enables either byte or word bus width on Port B,
depending
on the state of SIZE. A LOW selects long word operation. BM works with SIZE and BE
to select the bus size and endian arrangement for Port B. The level of BM must be
static throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A
and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA
are all synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B
and can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB
are all synchronized to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to HIGH transition of CLKA
to Read or Write
on Port A. The A
0–35
are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to HIGH transition of CLKB
to Read or Write
on Port B. The B
0–35
are in the high-impedance state when CSB is HIGH.
This is a dual-function pin.
In the CY Standard mode, the EFA function is selected.
EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A
0–35
outputs
available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of
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