PRELIMINARY
CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
256/512/1K/4K/16K x36 Unidirectional
Synchronous FIFO w/ Bus Matching
Features
• High-speed, low-power, Unidirectional, first-in first-out
(FIFO) memories w/ bus matching capabilities
• 256x36 (CY7C43623)
• 512x36 (CY7C43633)
• 1Kx36 (CY7C43643)
• 4Kx36 (CY7C43663)
• 16Kx36 (CY7C43683)
• 0.35-micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cycle
times)
• Low power
— I
CC
= 100 mA
— I
SB
= 5 mA
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost-Full and Al-
most-Empty flags
• Retransmit function
• Standard or FWFT mode user selectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Pin-compatible, feature enhanced, density upgrade to
IDT723623/33/43 family
• Easily expandable in width and depth
Logic Block Diagram
MBF1
CLKA
CSA
W/RA
ENA
MBA
RT
Input
Register
Output
Register
256/512/1K
4K/16K x36
Dual Ported
Memory
Bus Matching
Port-A
Control
Logic
Mail 1
Register
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
Port-B
Control
Logic
MRS1
MRS2
PRS
FIFO,
Mail1
Mail2
Reset
Logic
Write
Pointer
Read
Pointer
FF/IR
AF
Status
Flag Logic
EF/OR
AE
SPM
FS0/SD
FS1/SEN
A
0–35
36
36
Programmable Flag
Offset Registers
B
0–35
BE/FWFT
Timing
Mode
Mail 2
Register
MBF2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 2, 1998
PRELIMINARY
CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
Pin Configuration
CSA
FF/IR
NC
PRS
TQFP
Top View
V
CC
AF
NC
MBF2
MBA
MRS1
FS0/SD
GND
GND
FS1/SEN
MRS2
MBB
NC
EF/OR
NC
GND
CSB
W/RB
ENB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
MBF1
V
CC
AE
W/RA
ENA
CLKA
GND
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
BE/FWFT
GND
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
GND
A
11
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
CLKB
V
CC
V
CC
B
35
B
34
B
33
B
32
GND
GND
B
31
B
30
B
29
B
28
B
27
B
26
RT
B
25
B
24
BM
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
SIZE
V
CC
B
15
B
14
B
13
B
12
GND
B
11
B
10
CY7C43623
CY7C43633
CY7C43643
CY7C43663
CY7C43683
GND
A
5
A
4
A
3
SPM
V
CC
A
2
A
1
A
0
GND
B
0
B
1
2
GND
B
6
V
CC
B
7
B
8
B
9
A
9
A
8
A
7
A
6
B
2
B
3
B
4
B
5
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PRELIMINARY
Functional Description
The CY7C436x3 is a monolithic, high-speed, low-power,
CMOS Unidirectional Synchronous (clocked) FIFO memory
which supports clock frequencies up to 83 MHz and has read
access times as fast as 9 ns. Two independent
256/512/1K/4K/16K x 36 dual-port SRAM FIFOs on board
each chip buffer data in opposite directions. FIFO data on Port
B can be output in 36-bit, 18-bit, or 9-bit formats with a choice
of big- or little-endian configurations.
The CY7C436x3 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are in-
dependent of one another and can be asynchronous or coin-
cident. The enables for each port are arranged to provide a
simple Unidirectional interface between microprocessors
and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436x3: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array, config-
ures the FIFO for big- or little-endian byte arrangement and
selects serial flag programming, parallel flag programming, or
one of the three possible default flag offset settings, 8, 16, or
64. The FIFO also has a Master Reset pin, MRS1/MRS2.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings ex-
isting prior to Partial Reset (i.e., programming method and par-
tial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. The FIFO has its own independent
Partial Reset pin, PRS.
The CY7C436x3 have two modes of operation: In the CY Stan-
dard Mode, the first word written to an empty FIFO is deposited
into the memory array. A read operation is required to access
CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
that word (along with all other words residing in memory). In
the First Word Fall Through Mode (FWFT), the first long-word
(36-bit wide) written to an empty FIFO appears automatically
on the outputs, no read operation required (nevertheless, ac-
cessing subsequent words does necessitate a formal read re-
quest). The state of the FWFT/STAN pin during FIFO opera-
tion determines the mode in use.
The FIFO has a combined Empty/Output Ready flag (EF/OR)
and a combined Full/Input Ready flag (FF/IR). The EF and FF
functions are selected in the CY Standard Mode. EF indicates
whether the memory is full or not. The IR and OR functions are
selected in the First Word Fall Through Mode. IR indicates
whether or not the FIFO has available memory locations. OR
shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
The FIFO has a programmable Almost Empty flag (AE) and a
programmable Almost Full flag (AF). AE indicate when a se-
lected number of words written to FIFO memory achieve a
predetermined “almost empty state.” AF indicates when a se-
lected number of words written to the memory achieve a pre-
determined “almost full state.”
IR and AF are synchronized to the port clock that writes data
into its array. OR and AE are synchronized to the port clock
that reads data from its array. Programmable offset for AE and
AF are loaded in parallel using Port A or in serial via the SD
input. Three default offset settings are also provided. The AE
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AF threshold can be set at 8, 16, or 64 locations
from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. If any time, the FIFO is not actively performing a
function, the chip will automatically power down. During the
power-down state, supply current consumption (I
CC
) is at a
minimum. Initiating any operation (by activating control inputs)
will immediately take the device out of the power-down state.
The CY7C436x3 are characterized for operation from 0°C to
70°C. Input ESD protection is greater than 2001V, and latch-up
is prevented by the use of guard rings.
Selection Guide
CY7C43623/33/43/63/83-12
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
CC1
) (mA)
Commercial
Industrial
CY7C43623
Density
Package
256 x 36
128 TQFP
CY7C43633
512 x 36
128 TQFP
83
9
12
4
0
8
100
100
CY7C43643
1K x 36
128 TQFP
CY7C43663
4K x 36
128 TQFP
CY7C43623/33/43/63/83-15
66.7
10
15
5
0
8
100
100
CY7C43683
16K x 36
128 TQFP
3
PRELIMINARY
Pin Definitions
Signal Name
A
0–35
AE
Description
Port A Data
Almost Empty
Flag (Port B)
Almost Full Flag
I/O
I/O
O
CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
Function
36-bit Unidirectional data port for side A.
Programmable almost-empty flag synchronized to CLKA. It is LOW when the number
of words in the FIFO2 is less than or equal to the value in the almost-empty A offset
register, X.
Programmable almost-full flag synchronized to CLKA. It is LOW when the number of
empty locations in the FIFO is less than or equal to the value in the almost-full A offset
register, Y.
36-bit Unidirectional data port for side B.
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data
flow). A LOW on BE will select Little Endian operation. In this case, the least significant
byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port
B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH
on FWFT selects CY Standard mode, a LOW selects First Word Fall Through mode.
Once the timing mode has been selected, the level on FWFT must be static throughout
device operation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on the
state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM must be static
throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A and can
be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to the
LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B and can
be asynchronous or coincident to CLKA. FB/IR, EF/OR, AF, and AE are all synchro-
nized to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A
0–35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B
0–35
outputs are in the high-impedance state when CSB is HIGH.
This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF
indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function
is selected. OR indicates the presence of valid data on A
0–35
outputs, available for
reading. EF/OR is synchronized to the LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
on Port B.
This is a dual-function pin. In the CY Standard Mode, the FF function is selected. FF
indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function
is selected. IR indicates whether or not there is space available for writing to the FIFO
memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-
ming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag
offset programming method. Three offset register programming methods are available:
automatically load one of three preset values (8, 16, or 64), parallel load from Port A,
and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into
the X and Y registers. The number of bit writes required to program the offset registers
is 32 for the CY7C43623, 36 for the CY7C43633, 40 for the CY7C43643, 48 for the
CY7C43663, and 56 for the CY7C43683. The first bit write stores the Y-register MSB
and the last bit write stores the X-register LSB.
AF
O
B
0–35
BE/FWFT
Port B Data
Big Endian/First
Word Fall
Through Select
I/O
I
BM
Bus Match
Select (Port B)
I
CLKA
Port A Clock
I
CLKB
Port B Clock
I
CSA
CSB
EF/OR
Port A Chip
Select
Port B Chip
Select
Empty/Output
Ready Flag
(Port B)
Port A Enable
Port B Enable
Port B Full/Input
Ready Flag
I
I
O
ENA
ENB
FF/IR
I
I
O
FS1/SEN
Flag Offset
Select 1/Serial
Enable
Flag Offset
Select 0/Serial
Data
I
FS0/SD
I
4
PRELIMINARY
Pin Definitions
(continued)
Signal Name
MBA
MBB
Description
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register
Flag
I/O
I
I
CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
Function
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation.
When the B
0–35
outputs are active, a HIGH level on MBB selects data from the Mail1
register for output and a LOW level selects FIFO output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB
is HIGH. MBF1 is set HIGH following either a Master or Partial Reset.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA
is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO2.
A LOW on this pin initializes the FIFO read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
A LOW on this pin initializes the Mail2 Register.
A LOW on this pin initializes the FIFO read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or par-
allel), and programmable flag settings are all retained.
A LOW strobe on this pin will retransmit data on FIFO from the location of the write
pointer at the last Partial or Master reset.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must
be static throughout device operation.
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin
selects parallel programming or default offsets (8, 16, or 64).
A HIGH selects a write operation and a LOW selects a read operation on Port A for a
LOW-to-HIGH transition of CLKA. The A
0–35
outputs are in the HIGH impedance state
when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B for a
LOW-to-HIGH transition of CLKB. The B
0–35
outputs are in the HIGH impedance state
when W/RB is LOW.
MBF1
O
MBF2
Mail2 Register
Flag
O
MRS1
Master Reset
I
MRS2
PRS
Master Reset
Partial Reset
I
I
RT
SIZE
Retransmit
Bus Size Select
I
I
SPM
W/RA
Serial
Programming
Port A
Write/Read
Select
Port B
Write/Read
Select
I
I
W/RB
I
5
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