2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
Features
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Output frequency range: 8.3 MHz to 125 MHz
Input frequency range: 4.2 MHz to 62.5 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150 ps max output-output skew
PLL bypass mode
Spread Aware™
Output enable/disable
Pin compatible with MPC9774
Industrial temperature range: –40°C to +85°C
52-Pin 1.0-mm TQFP package
The CY29774 features two reference clock inputs and pro-
vides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs.
Bank A and Bank B divide the VCO output by 4 or 8 while Bank
C divides by 8 or 12 per SEL(A:C) settings, see
Functional
Table.
These dividers allow output to input ratios of 6:1, 4:1,
3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible out-
put can drive 50Ω series or parallel terminated transmission
lines. For series terminated transmission lines, each output
can drive one or two traces giving the device an effective
fanout of 1:28.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8.3 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback di-
vider, see
Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Description
The CY29774 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications.
Block Diagram
Pin Configuration
V C O _S E L
P L L_ E N
TC LK _ S EL
TC LK 0
T C LK 1
FB _IN
VCO_SEL
VDDQC
QC0
VDDQC
QC2
QB0
VDDQB
QC1
QC3
VSS
VSS
VSS
NC
PLL
20 0 -
5 00M H z
÷2
÷4
÷
2 /
÷
4
CLK
S TO P
SELA
÷2
/
÷4
CLK
STOP
Q A0
Q A1
Q A2
Q A3
Q A4
QB0
QB1
Q B2
QB3
QB4
QC0
QC1
QC2
QC3
52 51 50 49 48 47 46 45 44 43 42 41 40
VSS
MR#/OE
CLK_STP#
SELB
SELC
PLL_EN
SELA
TCLK_SEL
TCLK0
TCLK1
NC
VDD
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
VSS
QB1
VDDQB
QB2
VSS
QB3
VDDQB
QB4
FB_IN
VSS
FB_OUT
VDDFB
NC
CY29774
S E LB
÷4
/
÷6
CLK
STOP
S E LC
C LK _ S TP #
14 15 16 17 18 19 20 21 22 23 24 25 26
FB_SEL0
AVSS
VDDQA
QA4
QA3
VSS
QA2
FB_SEL1
VDDQA
QA1
VSS
VDDQA
QA0
÷4
/
÷6
/
÷8
/
÷12
F B _O U T
F B _S E L(1,0)
M R #/O E
Cypress Semiconductor Corporation
Document #: 38-07479 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised April 28, 2003
[+] Feedback
CY29774
Pin Description
[1]
Pin
9
10
16, 18, 21,
23, 25
32, 34, 36,
38, 40
44, 46, 48,
50
29
31
Name
TCLK0
TCLK1
QA(4:0)
QB(4:0)
QC(3:0)
FB_OUT
FB_IN
I/O
I, PD
I, PU
O
O
O
O
I, PU
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Description
LVCMOS/LVTTL reference clock input
LVCMOS/LVTTL reference clock input
Clock output bank A
Clock output bank B
Clock output bank C
Feedback clock output.
Connect to FB_IN for normal operation.
Feedback clock input.
Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference clock.
See
Table 1.
Output enable/disable input.
See
Table 2.
Clock stop enable/disable input.
See
Table 2.
PLL enable/disable input.
See
Table 2.
Reference select input.
See
Table 2.
VCO divider select input.
See
Table 2.
Frequency select input, Bank (A:C).
See
Table 3.
Feedback dividers select input.
See
Table 4.
2.5V or 3.3V Power supply for bank A output clocks
[2,3]
2.5V or 3.3V Power supply for bank B output clocks
[2,3]
2.5V or 3.3V Power supply for bank C output clocks
[2,3]
2.5V or 3.3V Power supply for feedback output clock
[2,3]
2.5V or 3.3V Power supply for PLL
[2,3]
2.5V or 3.3V Power supply for core and inputs
[2,3]
Analog Ground
Common Ground
2
3
6
8
52
7, 4, 5
20, 14
17, 22, 26
33, 37, 41
45, 49
28
13
12
15
1, 19, 24,
30, 35, 39,
43, 47, 51
11, 27, 42
MR#/OE
CLK_STP#
PLL_EN
TCLK_SEL
VCO_SEL
SEL(A:C)
FB_SEL(1,0)
VDDQA
VDDQB
VDDQC
VDDFB
AVDD
VDD
AVSS
VSS
I, PU
I, PU
I, PU
I, PD
I, PD
I, PD
I, PD
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VDD
VDD
VDD
VDD
VDD
VDD
Ground
Ground
NC
No Connection
Notes:
1. PU = Internal pull up, PD = Internal pull down
2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply
pins.
Document #: 38-07479 Rev. **
Page 2 of 9
[+] Feedback
CY29774
Table 1. Frequency Table
Feedback Output
Divider
÷8
÷12
÷16
÷24
÷32
÷48
VCO
Input Clock * 8
Input Clock * 12
Input Clock * 16
Input Clock * 24
Input Clock * 32
Input Clock * 48
Input Frequency Range
(AVDD = 3.3V)
25 MHz to 62.5 MHz
16.6 MHz to 41.6 MHz
12.5 MHz to 31.25 MHz
8.3 MHz to 20.8 MHz
6.25 MHz to 15.625 MHz
4.2 MHz to 10.4 MHz
Input Frequency Range
(AVDD = 2.5V)
25 MHz to 50 MHz
16.6 MHz to 33.3 MHz
12.5 MHz to 25 MHz
8.3 MHz to 16.6 MHz
6.25 MHz to 12.5 MHz
4.2 MHz to 8.3 MHz
Table 2. Function Table (configuration controls)
Control
TCLK_SEL
VCO_SEL
PLL_EN
MR#/OE
Default
0
0
1
1
0
TCLK0
VCO÷2 (high input frequency range)
Bypass mode, PLL disabled. The input clock
connects to the output dividers
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL feedback
loop is open and the VCO running at its minimum
frequency. The device is reset by the internal
power-on reset (POR) circuitry during power-up.
QA, QB, and QC outputs disabled in LOW state.
FB_OUT is not affected by CLK_STP#.
1
TCLK1
VCO÷4 (low input frequency range)
PLL enabled. The VCO output
connects to the output dividers
Outputs enabled
CLK_STP#
1
Outputs enabled
Table 3. Function Table (Bank A, B and C)
VCO_SEL
0
0
1
1
SELA
0
1
0
1
QA(4:0)
÷4
÷8
÷8
÷16
SELB
0
1
0
1
QB(4:0)
÷4
÷8
÷8
÷16
SELC
0
1
0
1
QC(3:0)
÷8
÷12
÷16
÷24
Table 4. Function Table (FB_OUT)
VCO_SEL
0
0
0
0
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
FB_OUT
÷8
÷16
÷12
÷24
÷16
÷32
÷24
÷48
Document #: 38-07479 Rev. **
Page 3 of 9
[+] Feedback
CY29774
.
Absolute Maximum Conditions
Parameter
V
DD
V
DD
V
IN
V
OUT
V
TT
LU
R
PS
T
S
T
A
T
J
Ø
JC
Ø
JA
ESD
H
FIT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Manufacturing test
Functional
Ripple Frequency < 100 kHz
Non Functional
Functional
Functional
Functional
Functional
Functional
Relative to V
SS
Relative to V
SS
Condition
Min.
–0.3
2.375
–0.3
–0.3
–
200
–
–65
–40
–
–
–
2000
10
Max.
5.5
3.465
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
÷
2
–
150
+150
+85
150
23
55
–
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Volts
ppm
DC Electrical Specifications
(V
DD
= 2.5V ± 5%, T
A
= –40°C to +85°C)
Parameter
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
DDA
I
DDQ
I
DD
C
IN
Z
OUT
Description
Input Voltage, Low
Input Voltage, High
Output Voltage, Low
[4]
Output Voltage, High
[4]
Input Current, Low
[5]
Input Current, High
[5]
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
Condition
LVCMOS
LVCMOS
I
OL
= 15 mA
I
OH
= –15 mA
V
IL
= V
SS
V
IL
= V
DD
A
VDD
only
All V
DD
pins except A
VDD
Outputs loaded @ 100 MHz
Min.
–
1.7
–
1.8
–
–
–
–
–
–
14
Typ.
–
–
–
–
–
–
5
–
135
4
18
Max.
0.7
V
DD
+0.3
0.6
–
–100
–
10
1
–
–
22
Unit
V
V
V
V
µA
µA
mA
mA
mA
pF
Ω
DC Electrical Specifications
(V
DD
= 3.3V ± 5%, T
A
= –40°C to +85°C)
Parameter
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
Description
Input Voltage, Low
Input Voltage, High
Output Voltage, Low
[4]
Output Voltage, High
[4]
Input Current, Low
[5]
Input Current, High
[5]
Condition
LVCMOS
LVCMOS
I
OL
= 24 mA
I
OL
= 12 mA
I
OH
= –24 mA
V
IL
= V
SS
V
IL
= V
DD
Min.
–
2.0
–
–
2.4
–
–
Typ.
–
–
–
–
–
–
–
Max.
0.8
V
DD
+0.3
0.55
0.30
–
–100
100
V
µA
µA
Unit
V
V
V
Notes:
4. Driving one 50Ω parallel terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50Ω series terminated
transmission lines.
5. Inputs have pull-up or pull-down resistors that affect the input current.
Document #: 38-07479 Rev. **
Page 4 of 9
[+] Feedback
CY29774
DC Electrical Specifications
(V
DD
= 3.3V ± 5%, T
A
= –40°C to +85°C) (continued)
Parameter
I
DDA
I
DDQ
I
DD
C
IN
Z
OUT
Description
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
Condition
A
VDD
only
All V
DD
pins except A
VDD
Outputs loaded @ 100 MHz
Min.
–
–
–
–
12
Typ.
5
–
225
4
15
Max.
10
1
–
–
18
Unit
mA
mA
mA
pF
Ω
AC Electrical Specifications
[6]
(V
DD
= 2.5V ± 5%, T
A
= –40°C to +85°C)
Parameter
f
VCO
f
in
Description
VCO Frequency
Input Frequency
÷8
Feedback
÷12
Feedback
÷16
Feedback
÷24
Feedback
÷32
Feedback
÷48
Feedback
Bypass mode (PLL_EN = 0)
f
refDC
t
r
, t
f
f
MAX
Input Duty Cycle
TCLK Input Rise/FallTime
Maximum Output Frequency
0.7V to 1.7V
÷4
Output
÷8
Output
÷12
Output
÷16
Output
÷24
Output
DC
t
r
, t
f
t
(φ)
t
sk(O)
tsk(B)
Output Duty Cycle
Output Rise/Fall times
Propagation Delay (static phase
offset)
Output-to-Output Skew
Bank-to-Bank Skew
0.7V to 1.8V
TCLK to FB_IN, does not
include jitter
Skew within Bank
Banks at same frequency
Banks at different frequency
t
PLZ, HZ
t
PZL, ZH
BW
t
JIT(CC)
t
JIT(PER)
t
JIT(φ)
t
LOCK
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth (–3 dB)
Cycle-to-Cycle Jitter
Same frequency
Multiple frequencies
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
Condition
Min.
200
25
16.6
12.5
8.3
6.3
4.2
0
25
–
50
25
16.6
12.5
8.3
45
0.1
–100
–
–
–
–
–
–
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.5 - 1.0
–
–
–
–
–
Max.
400
50
33.3
25
16.6
12.5
8.3
200
75
1.0
100
50
33.3
25
16.6
55
1.0
100
150
150
225
10
10
–
150
300
100
150
1
ps
ps
ms
ns
ns
MHz
ps
%
ns
ps
ps
ps
%
ns
MHz
Unit
MHz
MHz
Note:
6. AC characteristics apply for parallel output termination of 50Ω to V
TT
. Parameters are guaranteed by characterization and are not 100% tested.
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