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CY7C264-30PC

产品描述OTP ROM, 8KX8, 30ns, CMOS, PDIP24, 0.600 INCH, PLASTIC, DIP-24
产品类别存储    存储   
文件大小247KB,共14页
制造商Cypress(赛普拉斯)
下载文档 详细参数 全文预览

CY7C264-30PC概述

OTP ROM, 8KX8, 30ns, CMOS, PDIP24, 0.600 INCH, PLASTIC, DIP-24

CY7C264-30PC规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称Cypress(赛普拉斯)
零件包装代码DIP
包装说明0.600 INCH, PLASTIC, DIP-24
针数24
Reach Compliance Codenot_compliant
ECCN代码EAR99
最长访问时间30 ns
I/O 类型COMMON
JESD-30 代码R-PDIP-T24
JESD-609代码e0
内存密度65536 bit
内存集成电路类型OTP ROM
内存宽度8
功能数量1
端子数量24
字数8192 words
字数代码8000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织8KX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码DIP
封装等效代码DIP24,.6
封装形状RECTANGULAR
封装形式IN-LINE
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
认证状态Not Qualified
最大待机电流0.04 A
最大压摆率0.12 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED

文档预览

下载PDF文档
1
CY7C261
CY7C263/CY7C264
8K x 8 Power-Switched and Reprogrammable PROM
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
— 20 ns (Commercial)
— 25 ns (Military)
• Low power
— 660 mW (Commercial)
— 770 mW (Military)
• Super low standby power (7C261)
— Less than 220 mW when deselected
— Fast access: 20 ns
EPROM technology 100% programmable
Slim 300-mil or standard 600-mil packaging available
5V
±
10% V
CC
, commercial and military
Capable of withstanding greater than 2001V static
discharge
TTL-compatible I/O
Direct replacement for bipolar PROMs
the CY7C261 automatically powers down into a low-power
standby mode. It is packaged in a 300-mil-wide package. The
CY7C263 and CY7C264 are packaged in 300-mil-wide and
600-mil-wide packages respectively, and do not power down
when deselected. The reprogrammable packages are
equipped with an erasure window; when exposed to UV light,
these PROMs are erased and can then be reprogrammed.
The memory cells utilize proven EPROM floating-gate
technology and byte-wide intelligent programming algorithms.
The CY7C261, CY7C263, and CY7C264 are plug-in replace-
ments for bipolar devices and offer the advantages of lower
power, superior performance and programming yield. The
EPROM cell requires only 12.5V for the supervoltage and low
current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested
100%, as each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming the product will meet DC and AC specification
limits.
Read is accomplished by placing an active LOW signal on CS.
The contents of the memory location addressed by the
address line (A
0
−A
12
) will become available on the output lines
(O
0
−O
7
).
Functional Description
The CY7C261, CY7C263, and CY7C264 are high-perfor-
mance 8192-word by 8-bit CMOS PROMs. When deselected,
Logic Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
O
1
POWER DOWN
(7C261)
COLUMN
ADDRESS
O
3
ADDRESS
DECODER
O
4
O
5
ROW
ADDRESS
PROGRAM-
MABLE
ARRAY
COLUMN
MULTI-
PLEXER
O
7
Pin Configurations
DIP/Flatpack
Top View
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8 7C261 17
7C263
9 7C264 16
10
15
11
14
12
13
V
CC
A
8
A
9
A
10
CS
A
11
A
12
O
7
O
6
O
5
O
4
O
3
O
6
LCC/PLCC (OpaqueOnly)
Top View
4 3 2 1 28 27 26
25
5
24
6
23
7C261
7
22
8
7C263
21
9
20
10
19
11
12 1314151617 18
O1
O2
GND
NC
O3
O4
O5
A5
A6
A7
NC
VCC
A8
A9
A
4
A
3
A
2
A
1
A
0
NC
O
0
A
10
CS
A
11
A
12
NC
O
7
O
6
O
2
O
0
CS
For an 8K x 8 Registered PROM, see theCY7C265.
Cypress Semiconductor Corporation
Document #: 38-04010 Rev. *B
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised December 28, 2002
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