Latch-Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
6264-55
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[2]
V
CC
Operating
Supply Current
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA
Com’l
Ind’l
Com’l
Ind’l
15
20
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
0.8
+5
+5
–300
100
2.2
–0.5
–5
–5
Max.
6264-70
Min.
2.4
0.4
V
CC
0.8
+5
+5
–300
100
200
20
40
15
30
mA
mA
Max.
Unit
V
V
V
V
µA
µA
mA
mA
Automatic CE
1
Max. V
CC
, CE
1
> V
IH,
Power–Down Current Min. Duty Cycle=100%
Automatic CE
1
Max. V
CC
, CE
1
> V
CC
– 0.3V, Com’l
Power–Down Current V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
Ind’l
Shaded areas contain advance information.
Notes:
1. Minimum voltage is equal to–3.0V for pulse durations less than 30 ns.
2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 001-02367 Rev. **
Page 2 of 10
CY6264
Switching Characteristics
Over the Operating Range
[3]
6264-55
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
t
PU
t
PD
WRITE CYCLE
[6]
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE
1
LOW to Write End
CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[4]
WE HIGH to Low Z
5
50
40
30
40
0
0
25
25
0
20
5
70
60
50
55
0
0
40
35
0
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid
CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[4]
CE
1
LOW to Low Z
[5]
CE
2
HIGH to Low Z
CE
1
HIGH to High Z
[4, 5]
CE
2
LOW to High Z
CE
1
LOW to Power-Up
CE
1
HIGH to Power-Down
0
25
5
3
20
0
30
3
20
5
5
30
5
55
40
25
5
30
55
55
5
70
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
6264-70
Max.
Unit
Shaded areas contain advance information.
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
7
7
Unit
pF
pF
Notes:
3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
4. t
HZOE,
t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
5. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device.
6. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. Both signals must be LOW to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-02367 Rev. **
Page 3 of 10
CY6264
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R1 481Ω
5V
OUTPUT
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
R1 481Ω
ALL INPUT PULSES
3.0V
R2
255Ω
GND
10%
90%
90%
10%
< 5 ns
< 5 ns
(a)
(b)
THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Switching Waveforms
Read Cycle No. 1
[8, 9]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Read Cycle No. 2
[10, 11]
CE
1
t
RC
CE
2
OE
OE
t
ACE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
ICC
50%
ISB
HIGH
IMPEDANCE
DATA OUT
Notes:
8. Device is continuously selected. OE, CE = V
IL
. CE
2
= V
IH.
9. Address valid prior to or coincident with CE transition LOW.
10. WE is HIGH for read cycle.
11. Data I/O is High Z if OE = V
IH
, CE
1
= V
IH
, or WE = V
IL
.
Document #: 001-02367 Rev. **
Page 4 of 10
CY6264
Switching Waveforms
(continued)
Write Cycle No. 1 (WE Controlled)
[9, 11]
t
WC
ADDRESS
t
SCE1
CE
1
CE
2
t
SCE2
OE
t
AW
WE
t
SA
t
PWE
t
HA
t
SD
DATA IN
DATA VALID
IN
t
HZWE
DATA I/O
DATA UNDEFINED
t
HD
t
LZWE
HIGH IMPEDANCE
Write Cycle No. 2 (CE Controlled)
[9, 11, 12]
t
WC
ADDRESS
CE
1
t
SA
CE
2
t
SCE2
t
AW
t
PWE
WE
t
SD
DATA IN
DATA VALID
IN
t
HZWE
DATA I/O
HIGH IMPEDANCE
DATA UNDEFINED
t
HD
t
HA
t
SCE1
Note:
12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
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