CY7C924DX
200-MBaud HOTLink® Transceiver
Features
• Second-generation HOTLink® technology
• Fibre Channel and ESCON® compliant 8B/10B
encoder/decoder
• 10- or 12-bit pre-encoded data path (raw mode)
• 8- or 10-bit encoded data transport (using 8B/10B
coding)
• Parity check/generate
• Synchronous or asynchronous TTL parallel interface
• UTOPIA compatible host bus interface
• Embedded/Bypassable 256-character synchronous
FIFOs
• Integrated support for daisy-chain and ring topologies
• Domain or individual destination device addressing
• 50- to 200-MBaud serial signaling rate
• Internal PLLs with no external PLL components
• Dual differential PECL serial inputs
• Dual differential PECL serial outputs
• Compatible with fiber-optic modules and copper cables
• Built-In Self-Test (BIST) for link testing
• Link Quality Indicator
•
Single +5.0V
±10%
supply
• 100-pin TQFP
•
0.35µ CMOS technology
The transmit section of the CY7C924DX HOTLink can be con-
figured to accept either 8- or 10-bit data characters on each
clock cycle, and stores the parallel data into an internal Trans-
mit FIFO. Data is read from the Transmit FIFO and is encoded
using an embedded 8B/10B encoder to improve its serial
transmission characteristics. These encoded characters are
then serialized and output from two Positive ECL (PECL) com-
patible differential transmission line drivers at a bit-rate of 10
times the input reference clock.
The receive section of the CY7C924DX HOTLink accepts a
serial bit-stream from one of two PECL-compatible differential
line receivers and, using a completely integrated PLL Clock
Synchronizer, recovers the timing information necessary for
data reconstruction. The recovered bit stream is deserialized
and framed into characters, 8B/10B decoded, and checked for
transmission errors. Recovered decoded characters are re-
constructed into either 8- or 10-bit data characters, written to
an internal Receive FIFO, and presented to the destination
host system.
The integrated 8B/10B encoder/decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface. The embedded FIFOs may also be by-
passed to create a reference-locked serial transmission link.
For those systems requiring even greater FIFO storage capa-
bility, external FIFOs may be directly coupled to the
CY7C924DX device through the parallel interface without ad-
ditional glue-logic.
The TTL parallel I/O interface may be configured as either a
FIFO (configurable for UTOPIA emulation or for depth expan-
sion through external FIFOs) or as a pipeline register extender.
The FIFO configurations are optimized for transport of time-
independent (asynchronous) 8- or 10-bit character-oriented
data across a link. A Built-In Self-Test (BIST) pattern generator
and checker permits at-speed testing of the high-speed serial
data paths in both the transmit and receive sections, and
across the interconnecting links.
HOTLink devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed, point-to-
point serial links. Some applications include interconnecting
workstations, backplanes, servers, mass storage, and video
transmission equipment.
Functional Description
The 200-MBaud CY7C924DX HOTLink Transceiver is a point-
to-point communications building block allowing the transfer of
data over high-speed serial links (optical fiber, balanced, and
unbalanced copper transmission lines) at speeds ranging be-
tween 50 and 200 MBaud. The transmit section accepts par-
allel data of selectable width and converts it to serial data,
while the receiver section accepts serial data and converts it
to parallel data of selectable width.
Figure 1
illustrates typical
connections between two independent host systems and cor-
responding CY7C924DX parts. As a second generation
HOTLink device, the CY7C924DX provides enhanced levels of
technology, functionality, and integration over the field-proven
CY7B923/933 HOTLink.
Framer
Deserializer
Serializer
FIFO
Receive
Data
Receive
System Host
Decoder
8B/10B
Serial Link
8B/10B
Encoder
Transmit
FIFO
Transmit
Data
System Host
Control
CY7C924DX
Status
Serializer
FIFO
Transmit
Encoder
8B/10B
Data
Transmit
Serial Link
CY7C924DX
Deserializer
Framer
8B/10B
Decoder
Receive
FIFO
Control
Status
Receive
Data
Figure 1. HOTLink System Connections
HOTLink is a registered trademark of Cypress Semiconductor Corporation.
ESCON and IBM are registered trademarks of International Business Machines.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 14, 2000
CY7C924DX
CY7C924DX Transceiver Logic Block Diagram
TX
STATUS
3
TXDATA
CONTROL
11
13
4
Mode
Control
Output Register
Address Register
TXCLK
MODE
REFCLK
9
RX
STATUS
RXDATA
RXCLK
13
Output Register
MUX
MUX
Flags
Mode
Receive
FIFO
Input Register
Flags
Transmit
FIFO
Transmit
PLL Clock
Multiplier
MUX
Receive
Formatter
Pipeline Register
Byte-Unpacker
Parity Generation
Address Matching
Elasticity
Buffer
MUX
Transmit
Formatter
Pipeline Register
Parity Checker
Byte-Packer
CONTROL
AM*
TXEN*
RXEN*
TXSTOP*
TXRST*
RXRST*
RFEN
TXBISTEN*
RXBISTEN*
RESET*[1:0]
MODE
RANGESEL
SPDSEL
RXMODE[1:0]
FIFOBYP*
EXTFIFO
ENCBYP*
BYTE8/10*
TEST*
Clock
Divider
RXSTATUS
LFI*
RXEMPTY*
RXHALF*
RXFULL*
TX STATUS
TXEMPTY*
TXHALF*
TXFULL*
Receive
Control
State
Machine
BIST LFSR
8B/10B Decoder
BIST LFSR
8B/10B Encoder
MUX
Transmit
Control
State
Machine
Deserializer
Framer
Serial Shifter
Bit Clock
Receive
Clock/Data
Recovery
Bit Clock
LOOPBACK
CONTROL
DLB[1:0]
LOOPTX
3
LOOPBACK
CONTROL
Routing Matrix
Signal
Validation
OUTA
INA
OUTB
CURSETB
CURSETA
INB
A/B*
CARDET
2
CY7C924DX
Pin Configuration
RXBISTEN*
CURSETB
CURSETA
TQFP
Top View
OUTB+
OUTB–
OUTA+
OUTA–
VDDA
VDDA
VDDA
VDDA
VDDA
VSSA
VSSA
VSSA
VSSA
VSSA
INA+
INB+
INA–
INB–
CARDET
VDDA
VSSA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TEST*
A/B*
LFI*
DLB[1]
DLB[0]
LOOPTX
TXBISTEN*
RXCLK
TXSTOP*
RXFULL*
VSS
REFCLK
VSS
VDD
VSS
TXRST*
VDD
TXEN*
RXHALF*
TXSC/D*
RXEMPTY*
TXDATA[0]
RXSOC/RXDATA[11]
RXMODE[1]
RXMODE[0]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSSA
75
74
73
72
71
70
69
68
67
66
65
64
SPDSEL
RANGESEL
RFEN
TXFULL*
AM*
TXHALF*
RXEN*
TXCLK
RXRST*
VSS
RXSC/D*
VDD
VSS
VDD
RXDATA[0]
TXEMPTY*
RXDATA[1]
TXSOC/PAREN/TXDATA[11]
VSS
TXSVS/TXDATA[10]
VDD
TXHALT*/TXDATA[9]
RXDATA[2]
RESET*[1]
RESET*[0]
CY7C924DX
63
62
61
60
59
58
57
56
55
54
53
52
51
TXINT/TXOPIN/TXDATA[8]
RXINT/RXOP/RXDATA[8]
RXDATA[9]
VSS
VSS
RXRVS/RXDATA[10]
VSS
VSS
TXDATA[1]
TXDATA[2]
RXDATA[7]
RXDATA[6]
RXDATA[5]
RXDATA[4]
RXDATA[3]
TXDATA[3]
TXDATA[4]
TXDATA[5]
TXDATA[6]
TXDATA[7]
FIFOBYP*
EXTFIFO
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +6.5V
DC Voltage Applied to Outputs
in High-Z State .........................................–0.5V to V
DD
+0.5V
Output Current into TTL Outputs (LOW)...................... 30 mA
DC Input Voltage ..................................... –0.5V to V
DD
+0.5V
Static Discharge Voltage...............................................> 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current...........................................................> 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
5.0V
±
10%
5.0V
±
10%
3
BYTE8/10*
ENCBYP*
VDD
CY7C924DX
Pin Descriptions
CY7C924DX HOTLink Transceiver
Pin #
Name
I/O Characteristics
TTL input, sampled
on TXCLK↑ or
REFCLK↑,
Internal Pull-Up
Parallel Transmit Data Input.
Bus width can be configured to accept either 8- or 10-bit characters.
When the encoder is bypassed (ENCBYP* is LOW), TXDATA[7:0] functions as
the least significant eight bits of the 10- or 12-bit pre-encoded transmit char-
acter.
Transmit Interrupt Input.
This input is only interpreted if both the Transmit FIFO and Encoder are en-
abled.
Upon any state-change (0→1 or 1→0) in TXINT, a character is forced into the
transmit encoder and shifter prior to accessing the next Transmit FIFO con-
tents. This signal is routed around, not through, the Transmit FIFO.
When TXINT transitions from 0→1, a C0.0 (K28.0) special code is sent. When
TXINT transitions from 1→0, a C3.0 (K28.3) special code is sent. These spe-
cial codes force a similar signal transition on the RXINT output of an attached
CY7C924DX HOTLink Transceiver.
When the Transmit FIFO is bypassed (FIFOBYP* is LOW) and the encoder is
enabled (ENCBYP* is HIGH), this input is the ODD parity input associated with
the TXDATA[7:0], TXSC/D*, and TXSVS inputs when parity is enabled, and
ignored otherwise.
When the encoder is bypassed (ENCBYP* is LOW), TXDATA[8] functions as
the 9th bit of the 10- or 12-bit pre-encoded transmit character.
54
TXHALT*/
TXDATA[9]
TTL input, sampled
on TXCLK↑ or
REFCLK↑,
Internal Pull-Up
Transmit FIFO Halt Immediate Input.
When TXHALT* is asserted LOW, transmission of data is suspended and the
HOTLink transmits pad characters (K28.5). When TXHALT* is deasserted
HIGH, normal data processing proceeds.
When the encoder is bypassed (ENCBYP* is LOW), TXDATA[9] functions as
the 10th bit of the 10- or 12-bit pre-encoded transmit character.
TXPER
TTL output, changes Transmit Parity Error Output.
following TXCLK↑ or When the FIFOs are bypassed (FIFOBYP* is LOW) and the Encoder is en-
REFCLK↑
abled (ENCBYP* is HIGH) this pin is an output and indicates that parity errors
have been found in the TXDATA[7:0], TXSC/D*, TXSVS, and TXOPIN inputs.
TTL input, sampled
on TXCLK↑ or
REFCLK↑,
Internal Pull-Up
Transmit Send Violation Symbol input.
When the Transmit FIFO is enabled, this input is interpreted along with TXSOC
and TXSC/D* (see
Table 2
for details).
When the encoder is bypassed (ENCBYP* is LOW) and in 10-bit mode
(BYTE8/10* is LOW), TXDATA[10] functions as the 11th bit of the 12-bit pre-
encoded transmit character.
Transmit Start of Cell Input.
When the Transmit FIFO is enabled (FIFOBYP* is HIGH), this input is used as
a message frame delimiter to indicate the beginning of a data packet. It is
interpreted along with TXSVS and TXSC/D* (see
Table 2
for details).
When the Transmit FIFO is bypassed (FIFOBYP* is LOW), this input is the
Parity Enable input which enables ODD parity checking of the TXDATA[7:0],
TXSC/D*, TXSVS, and TXOPIN inputs.
When the encoder is bypassed (ENCBYP* is LOW) and in 10-bit mode
(BYTE8/10* is LOW), TXDATA[11] functions as the 12th bit (MSB) of the 12-bit
pre-encoded transmit character.
Signal Description
Transmit Path Signals
44, 42, TXDATA[7:0]
40, 36,
34, 32,
30, 22
46
TXINT/
TXOPIN/
TXDATA[8]
TTL input, sampled
on TXCLK↑ or
REFCLK↑,
Internal Pull-Up
56
TXSVS/
TXDATA[10]
58
TXSOC/
PAREN/
TXDATA[11]
TTL input, sampled
on TXCLK↑ or
REFCLK↑,
Internal Pull-Up
4
CY7C924DX
Pin Descriptions
(continued)
CY7C924DX HOTLink Transceiver
Pin #
20
Name
TXSC/D*
I/O Characteristics
TTL input, sampled
on TXCLK↑ or
REFCLK↑,
Internal Pull-Up
TTL input, sampled
on TXCLK↑ or
REFCLK↑,
Internal Pull-Up
TTL input, sampled
on TXCLK↑,
Internal Pull-Up
Signal Description
Transmit Special Character or Data Select Input.
When the Transmit FIFO is enabled, this input is interpreted along with TXSVS
and TXSOC (see
Table 2
for details).
When the encoder is bypassed (ENCBYP* is LOW) TXSC/D* is ignored.
Transmit Enable Input.
Data enable for the TXDATA[11:0] data bus write operations. Active HIGH
when configured for Cascade timing, active LOW when configured for UTOPIA
timing.
Transmit Stop on Start_Of_Cell Input.
While the Transmit FIFO is enabled, this signal is used to prevent queued data
characters from being serially transmitted. While TXSTOP* is deasserted
(HIGH), data flows through the Transmit FIFO without interruption. When
TXSTOP* is asserted (LOW), data transfers continue until a TXSOC bit is
detected in the character stream, at which point data transmission ceases. If
TXSTOP* is momentarily deasserted and then reasserted, a single “cell” (de-
limited by SOC bits) is transmitted. Stopped transfers and empty FIFO condi-
tions are padded with C5.0 (K28.5) characters.
When the transmit FIFO is bypassed (FIFOBYP* = LOW), TXSTOP* has no
function. This input can be left open or tied HIGH.
68
TXCLK
TTL clock input,
Internal Pull-Up
3-state TTL output,
changes following
TXCLK↑ or
REFCLK↑
Transmit FIFO Clock.
The input clock for the parallel interface when the Transmit FIFO is enabled.
Used to sample all Transmit FIFO related interface signals.
Transmit FIFO Full Status Flag.
Active LOW when configured for UTOPIA timing, active HIGH when configured
for Cascade timing.
When the Transmit FIFO is enabled (FIFOBYP* is HIGH), TXFULL* Indicates
a Transmit FIFO full condition. When TXFULL* is first asserted, the Transmit
FIFO can accept a minimum of eight additional write cycles without loss of
data.
When the Transmit FIFO is bypassed (FIFOBYP* is LOW), with RANGESEL
HIGH or SPDSEL LOW, TXFULL* toggles at half the REFCLK rate to provide
a character rate indication. Data can be accepted when TXFULL* indicates a
non-full condition.
70
TXHALF*
3-state TTL output,
changes following
TXCLK↑ or
REFCLK↑
3-state TTL output,
changes following
TXCLK↑ or
REFCLK↑
Transmit FIFO Half-full Status Flag. Active LOW.
When the Transmit FIFO is enabled, TXHALF* is asserted LOW when the
Transmit FIFO is
≥
half full (128 characters).
TXHALF* is only set to High-Z state by the assertion of RESET*[1:0] LOW.
Transmit FIFO Empty Status Flag.
Active LOW when configured for UTOPIA timing, active HIGH when configured
for Cascade timing.
When the Transmit FIFO is enabled, TXEMPTY* is asserted either when no
data has been loaded into the Transmit FIFO, or when the Transmit FIFO has
been emptied by either a Transmit FIFO reset or by the normal transmission of
the FIFO contents.
When TXBISTEN* is asserted LOW, TXEMPTY* becomes the transmit BIST-
loop counter indicator (regardless of the logic state of FIFOBYP*). In this mode
TXEMPTY* is asserted for one TXCLK period at the end of each transmitted
BIST sequence.
When the Transmit FIFO is bypassed, TXEMPTY* is asserted to indicate that
the transmitter can accept data. TXEMPTY* is also used as a BIST progress
indicator when TXBISTEN* is asserted.
18
TXEN*
9
TXSTOP*
72
TXFULL*
60
TXEMPTY*
5
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