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CY8C24094, CY8C24794
CY8C24894, CY8C24994
PSoC
®
Programmable System-on-Chip
1. Features
■
■
■
XRES pin to support In-System Serial Programming (ISSP) and
external reset control in CY8C24894
Powerful Harvard-architecture processor
❐
M8C processor speeds to 24 MHz
❐
Two 8 × 8 multiply, 32-bit accumulate
❐
Low power at high speed
❐
3 V to 5.25 V operating voltage
❐
Industrial temperature range: –40 °C to +85 °C
❐
USB temperature range: –10 °C to +85 °C
Advanced peripherals (PSoC Blocks)
❐
Six rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐
Four digital PSoC blocks provide:
• 8 to 32-bit timers, counters, and pulse width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Full-duplex universal asynchronous receiver transmitter
(UART)
• Multiple serial peripheral interface (SPI) masters or slaves
• Connectable to all general purpose I/O (GPIO) pins
❐
Complex peripherals by combining blocks
❐
Capacitive sensing application (CSA) capability
Full-Speed USB (12 Mbps)
❐
Four unidirectional endpoints
❐
One bidirectional control endpoint
❐
USB 2.0 compliant
❐
Dedicated 256 byte buffer
❐
No external crystal required
Flexible on-chip memory
❐
16 KB flash program storage 50,000 erase and write cycles
❐
1 KB static random access memory (SRAM) data storage
❐
ISSP
❐
Partial flash updates
❐
Flexible protection modes
❐
Electrically erasable programmable read-only memory
(EEPROM) emulation in flash
Programmable pin configurations
❐
25 mA sink, 10 mA source on all GPIOs
❐
Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIOs
❐
Up to 48 analog inputs on GPIO
❐
Two 33 mA analog outputs on GPIO
❐
Configurable interrupt on all GPIOs
®
■
Precision, programmable clocking
❐
Internal ±4% 24- and 48- MHz oscillator
❐
Internal oscillator for watchdog and sleep
❐
0.25% accuracy for USB with no external components
Additional system resources
2
❐
I C slave, master, and multi-master to 400 kHz
❐
Watchdog and sleep timers
❐
User-configurable low-voltage detection (LVD)
2. Logic Block Diagram
Port 7
Port 5 Port 4 Port 3
Port 2 Port 1 Port 0 Analog
Drivers
■
System Bus
Global Digital Interconnect
Global Analog Interconnect
Flash16 KB
Sleep and
Watchdog
PSoC CORE
SRAM
1K
Interrupt
Controller
SROM
CPU Core (M8C)
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Ref.
■
Analog
Block
Array
■
Digital
2
Decimator
Clocks MACs Type 2
I
2
C
POR and LVD Internal
Voltage
System Resets
Ref.
USB
Analog
Input
Muxing
SYSTEM RESOURCES
■
Cypress Semiconductor Corporation
Document Number: 38-12018 Rev. *V
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 27, 2010
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CY8C24094, CY8C24794
CY8C24894, CY8C24994
3. Contents
Features............................................................................... 1
Logic Block Diagram.......................................................... 1
Contents .............................................................................. 2
PSoC Functional Overview................................................ 3
The PSoC Core ............................................................. 3
The Digital System ........................................................ 3
The Analog System ....................................................... 4
Additional System Resources ....................................... 5
PSoC Device Characteristics ........................................ 5
Getting Started.................................................................... 5
Application Notes .......................................................... 5
Development Kits .......................................................... 5
Training ......................................................................... 5
CYPros Consultants ...................................................... 5
Solutions Library............................................................ 5
Technical Support ......................................................... 5
Development Tools ............................................................ 6
PSoC Designer Software Subsystems.......................... 6
Designing with PSoC Designer ......................................... 7
Select User Modules ..................................................... 7
Configure User Modules................................................ 7
Organize and Connect .................................................. 7
Generate, Verify, and Debug......................................... 7
Pin Information ................................................................... 8
56-Pin Part Pinout ......................................................... 8
56-Pin Part Pinout (with XRES)..................................... 9
68-Pin Part Pinout ....................................................... 10
68-Pin Part Pinout (On-Chip Debug)........................... 11
100-Ball VFBGA Part Pinout ....................................... 12
100-Ball VFBGA Part Pinout (On-Chip Debug)........... 14
100-Pin Part Pinout (On-Chip Debug)......................... 16
Register Reference...........................................................
Register Conventions ..................................................
Register Mapping Tables ............................................
Register Map Bank 0 Table: User Space ....................
Register Map Bank 1 Table: Configuration Space ......
Electrical Specifications ..................................................
Absolute Maximum Ratings.........................................
Operating Temperature ...............................................
DC Electrical Characteristics.......................................
AC Electrical Characteristics .......................................
Packaging Dimensions ....................................................
Thermal Impedance ....................................................
Solder Reflow Peak Temperature ...............................
Development Tool Selection ...........................................
Software ......................................................................
Development Kits ........................................................
Evaluation Tools..........................................................
Device Programmers...................................................
Accessories (Emulation and Programming) ................
Ordering Information........................................................
Ordering Code Definitions ...........................................
Document Conventions ...................................................
Acronyms Used ...........................................................
Units of Measure .........................................................
Numeric Naming..........................................................
Document History Page ...................................................
Sales, Solutions, and Legal Information ........................
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Document Number: 38-12018 Rev. *V
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4. PSoC Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional MCU-based system components with one low-cost
single-chip programmable component. A PSoC device includes
configurable blocks of analog and digital logic, and
programmable interconnect. This architecture makes it possible
for you to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast central processing unit (CPU), flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts.
The PSoC architecture, shown in
“”
on page 1, consists of four
main areas: the core, the system resources, the digital system,
and the analog system. configurable global bus resources allow
combining all of the device resources into a complete custom
system. Each CY8C24x94 PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 GPIOs are also included. The GPIOs provide
access to the global digital and analog interconnects.
4.2 The Digital System
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that is used alone or combined with
other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations
include:
■
■
■
■
■
■
■
■
■
■
PWMs (8- to 32-bit)
PWMs with dead band (8- to 32-bit)
Counters (8- to 32-bit)
Timers (8- to 32-bit)
UART 8-bit with selectable parity
SPI master and slave
I
2
C slave and multi-master
CRC/generator (8-bit)
IrDA
PRS generators (8- to 32-bit)
4.1 The PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO) and internal low speed oscillator (ILO). The CPU
core, called the M8C, is a powerful processor with speeds up to
24 MHz. The M8C is a four-million instructions per second
(MIPS) 8-bit Harvard-architecture microprocessor.
System resources provide these additional capabilities:
■
■
■
■
■
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in
Table 4-1
on page 5.
Figure 4-1. Digital System Block Diagram
Port 7
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Digital clocks for increased flexibility
I
2
C functionality to implement an I
2
C master and slave
An internal voltage reference, multi-master, that provides an
absolute value of 1.3 V to a number of PSoC subsystems
A switch mode pump (SMP) that generates normal operating
voltages from a single battery cell
Various system resets supported by the M8C
Digital Clocks
From Core
To System Bus
To Analog
System
Row Input
Configuration
The digital system consists of an array of digital PSoC blocks that
may be configured into any number of digital peripherals. The
digital blocks are connected to the GPIOs through a series of
global buses. These can route any signal to any pin, freeing
designs from the constraints of a fixed peripheral controller.
The analog system consists of four analog PSoC blocks,
supporting comparators, and analog-to-digital conversion up to
10 bits of precision.
DIGITAL SYSTEM
Digital PSoC Block Array
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
Row Output
Configuration
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 38-12018 Rev. *V
Page 3 of 51
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4.3 The Analog System
The analog system is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are as follows.
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Figure 4-2. Analog System Block Diagram
A ll IO
(E x c e p t P o r t 7 )
P 0 [7 ]
P 0 [5 ]
P 0 [3 ]
P 0 [1 ]
AGNDIn RefIn
Mux Bus
Analog
P 0 [6 ]
P 0 [4 ]
P 0 [2 ]
P 0 [0 ]
P 2 [6 ]
ADCs (up to two, with 6- to 14-bit resolution, selectable as
incremental, delta sigma, and SAR)
Filters (2 and 4 pole band-pass, low-pass, and notch)
Amplifiers (up to two, with selectable gain to 48x)
Instrumentation amplifiers (one with selectable gain to 93x)
Comparators (up to two, with 16 selectable thresholds)
DACs (up to two, with 6- to 9-bit resolution)
Multiplying DACs (up to two, with 6- to 9-bit resolution)
High current output drivers (two with 30 mA drive as a PSoC
core resource)
1.3-V reference (as a system resource)
DTMF dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
P 2 [3 ]
P 2 [4 ]
P 2 [2 ]
P 2 [0 ]
P 2 [1 ]
A C I 0 [1 :0 ]
A C I 1 [1 :0 ]
A r r a y In p u t
C o n f ig u r a t io n
B lo c k
A rray
AC B00
A SC 10
ASD20
A C B 01
A SD 11
A SC 21
A n a lo g R e f e r e n c e
In t e r f a c e t o
D ig it a l S y s t e m
R e fH i
R e fL o
AGND
R e fe r e n c e
G e n e ra to rs
A G N D In
R e fIn
B andgap
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in
Figure 4-2.
M 8 C In t e r f a c e ( A d d r e s s B u s , D a t a B u s , E t c .)
4.3.1 The Analog Multiplexer System
The analog mux bus can connect to every GPIO pin in ports 0-5.
Pins are connected to the bus individually or in any combination.
The bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. It is split into two
sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Switch-control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
Track pad, finger sensing
Chip-wide mux that enables analog input from up to 48 I/O pins
Crosspoint connection between any I/O pin combinations
Document Number: 38-12018 Rev. *V
Page 4 of 51
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