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CY7C4425/4205/4215
CY7C4225/4235/4245
64/256/512/1K/2K/4K x 18 Synchronous FIFOs
Features
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■
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■
■
■
■
■
■
■
■
■
■
■
■
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■
Functional Description
The CY7C42X5 are high speed, low power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All are
18 bits wide and are pin/functionally compatible to IDT722X5.
The CY7C42X5 can be cascaded to increase FIFO depth.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a write enable
pin (WEN). When WEN is asserted, data is written into the FIFO
on the rising edge of the WCLK signal. While WEN is held active,
data is continually written into the FIFO on each cycle. The
output port is controlled in a similar manner by a free-running
read clock (RCLK) and a read enable pin (REN). In addition, the
CY7C42X5 have an output enable pin (OE). The read and write
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write
applications. Clock frequencies up to 100 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI, RXI),
cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of
the next device, and the WXO and RXO pins of the last device
should be connected to the WXI and RXI pins of the first device.
The FL pin of the first device is tied to VSS and the FL pin of all
the remaining devices should be tied to VCC.
The CY7C42X5 provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see Table 2). The Half Full flag
shares the WXO pin. This flag is valid in the standalone and
width-expansion configurations. In the depth expansion, this pin
provides the expansion out (WXO) information that is used to
signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one clock
cycle to the next. As mentioned previously, the Almost
Empty/Almost Full flags become synchronous if the
VCC/SMODE is tied to VSS. All configurations are fabricated
using an advanced 0.65m N-Well CMOS technology. Input ESD
protection is greater than 2001V, and latch-up is prevented by
the use of guard rings.
High speed, low power, first-in first-out (FIFO) memories
64 x 18 (CY7C4425)
256 x 18 (CY7C4205)
512 x 18 (CY7C4215)
1K x 18 (CY7C4225)
2K x 18 (CY7C4235)
4K x 18 (CY7C4245)
High speed 100 MHz operation (10 ns read/write cycle time)
Low power (I
CC
= 45 mA)
Fully asynchronous and simultaneous read and write operation
Empty, Full, Half Full, and Programmable Almost Empty/Almost
Full status flags
TTL compatible
Retransmit function
Output Enable (OE) pin
Independent read and write enable pins
Center power and ground for reduced noise
Supports free running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability
Available in 64 pin 14 x 14 TQFP, 64 pin 10 x 10 TQFP, and
68-pin PLCC
Cypress Semiconductor Corporation
Document Number: 001-45652 Rev. **
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 02, 2008
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CY7C4425/4205/4215
CY7C4225/4235/4245
Logic Block Diagram
D
0–17
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
RAM
ARRAY
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
FF
EF
PAE
PAF
SMODE
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
TRI–STATE
OUTPUT REGISTER
READ
CONTROL
OE
Q
0–17
RCLK
REN
Pin Configuration
Figure 1.
TQFP (Top View)
V
CC
/SMODE
D
16
D
17
GND
RCLK
REN
LD
OE
RS
V
CC
Figure 2. PLCC (Top View)
GND
RCLK
GND
REN
EF
V
CC
Q
17
D
17
D
15
GND
Q
15
RS
V
CC
Q
16
D
16
GND
EF
Q
17
Q
16
GND
Q
15
9 8 7
D
14
D
13
D
12
D
11
D
10
D
9
V
CC
D
8
GND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
6 5
4
LD
OE
3
2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
CC
/SMODE
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
V
CC
Q
6
Q
5
GND
Q
4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
2728 2930 3132 33 34 35 36 37 38 3940 4142 43
PAE
PAF
WXI
V
CC
RXI
FF
WXO/HF
RXO
FL/RT
WCLK
WEN
GND
Q
0
Q
1
Q
2
Q
3
PAF
RXI
FF
WXO/HF
RXO
Q
0
Q
1
GND
Q
2
PAE
FL/RT
WCLK
WEN
WXI
V
CC
Document Number: 001-45652 Rev. **
Q
3
V
CC
Page 2 of 22
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CY7C4425/4205/4215
CY7C4225/4235/4245
Selection Guide
Description
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Operating Current (I
CC2
) (mA) @ 20MHz
Commercial
Industrial
Parameter
Density
Packages
CY7C4425
64 x 18
CY7C4205
256 x 18
-10
100
8
10
3
0.5
8
45
50
CY7C4215
512 x 18
-15
66.7
10
15
4
1
10
45
50
CY7C4225
1K x 18
-25
40
15
25
6
1
15
45
50
CY7C4235
2K x 18
-35
28.6
20
35
7
2
20
45
50
CY7C4245
4K x 18
64-pin TQFP
64-pin TQFP
64-pin TQFP
64-pin TQFP
64-pin TQFP
64-pin TQFP
(14 x 14, 10 x 10) (14 x 14, 10 x 10) (14 x 14, 10 x 10) (14 x 14, 10 x 10) (14 x 14, 10 x 10) (14 x 14, 10 x 10)
68-pin PLCC
68-pin PLCC
68-pin PLCC
68-pin PLCC
68-pin PLCC
68-pin PLCC
(10 x 10)
(10 x 10)
(10 x 10)
(10 x 10)
(10 x 10)
(10 x 10)
Pin Definitions
Signal Name
D
0−17
Q
0−17
WEN
REN
WCLK
RCLK
Description
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
Read Clock
IO
I
O
I
I
I
I
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
Dual-Mode Pin. Single device or width expansion - Half Full status flag. Cascaded – Write
Expansion Out signal, connected to WXI of next device.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is asynchronous when V
CC
/SMODE is tied to V
CC
;
it is synchronized to RCLK when V
CC
/SMODE is tied to V
SS
.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
CC
/SMODE is tied to V
CC
;
it is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
When LD is LOW, D
0−17
(O
0−17
) are written (read) into (from) the program-
mable-flag-offset register.
Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to V
SS
;
all other devices will have FL tied to V
CC
. In standard mode of width expansion, FL
is tied to V
SS
on all devices. Not Cascaded – Tied to V
SS
. Retransmit function is also
available in standalone mode by strobing RT.
Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to V
SS
.
Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to V
SS
.
Function
WXO/HF
EF
FF
PAE
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
O
O
O
O
PAF
O
LD
FL/RT
I
I
WXI
RXI
Write Expansion
Input
Read Expansion
Input
I
I
Document Number: 001-45652 Rev. **
Page 3 of 22
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CY7C4425/4205/4215
CY7C4225/4235/4245
Pin Definitions
(continued)
Signal Name
RXO
RS
OE
V
CC
/SMODE
Description
Read Expansion
Output
Reset
Output Enable
Synchronous
Almost Empty/
Almost Full Flags
IO
O
I
I
I
Function
Cascaded – Connected to RXI of next device.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Dual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to V
CC
.
Synchronous Almost Empty/Almost Full flags – tied to V
SS
. (Almost Empty synchro-
nized to RCLK, Almost Full synchronized to WCLK.)
Architecture
The CY7C42X5 consists of an array of 64 to 4K words of 18 bits
each (implemented by a dual-port array of SRAM cells), a read
pointer, a write pointer, control signals (RCLK, WCLK, REN,
WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C42X5
also includes the control signals WXI, RXI, WXO, RXO for depth
expansion.
Programming
The CY7C42X5 devices contain two 12-bit offset registers. Data
present on D
0–11
during a program write will determine the
distance from Empty (Full) that the Almost Empty (Almost Full)
flags become active. If the user elects not to program the FIFO’s
flags, the default offset values are used (see
Table 2).
When the
Load LD pin is set LOW and WEN is set LOW, data on the inputs
D
0–11
is written into the Empty offset register on the first
LOW-to-HIGH transition of the write clock (WCLK). When the LD
pin and WEN are held LOW then data is written into the Full offset
register on the second LOW-to-HIGH transition of the Write
Clock (WCLK). The third transition of the Write Clock (WCLK)
again writes to the Empty offset register (see
Table 1).
Writing all
offset registers does not have to occur at one time. One or two
offset registers can be written and then, by bringing the LD pin
HIGH, the FIFO is returned to normal read/write operation. When
the LD pin is set LOW, and WEN is LOW, the next offset register
in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Table 1. Write Offset Register
LD
0
WEN
0
WCLK
[1]
Selection
Writing to offset registers:
Empty Offset
Full Offset
No Operation
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. In order for the FIFO to reset to its
default state, a falling edge must occur on RS and the user must
not read or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the D
0-17
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory will be presented on the Q
0−17
outputs. New data
will be presented on each rising edge of RCLK while REN is
active LOW and OE is LOW. REN must set up t
ENS
before RCLK
for it to be a valid read function. WEN must occur t
ENS
before
WCLK for it to be a valid write function.
An Output Enable (OE) pin is provided to three-state the Q
0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q
0−17
outputs
after t
OE
. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
0−17
outputs even
after additional reads occur.
0
1
1
0
Write Into FIFO
1
1
No Operation
Note:
1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document Number: 001-45652 Rev. **
Page 4 of 22
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