UNISONIC TECHNOLOGIES CO., LTD
4052
DIFFERENTIAL 4-CHANNEL
ANALOG MULTIPLEXERS/
DEMULTIPLEXERS
DESCRIPTION
The UTC
4052
is differential 4-channel analog multiplexers/
demultiplexers for application as digitally–controlled analog switches.
The device has two binary control inputs and an inhibit input. It
feature low ON impedance and very low OFF leakage current.
Control of analog signals up to the complete supply voltage range
can be achieved.
CMOS IC
FEATURES
* Wide Analog Voltage Range: V
DD
–V
EE
= 3V~18V.
(Note: V
EE
must be≦V
SS
)
* Break-Before-Make Switching Eliminates Channel Overlap.
* Linearized Transfer Characteristics
* Implement an DP4T Switch Effectively.
* Pin to Pin Replacement for CD4052
ORDERING INFORMATION
Normal
4052-D16-T
4052-P16-R
4052-S16-T
4052-S16-R
Ordering Number
Lead Free Plating
4052L-D16-T
4052L-P16-R
4052L-S16-T
4052L-S16-R
Halogen Free
4052G-D16-T
4052G-P16-R
4052G-S16-T
4052G-S16-R
Package
DIP-16
TSSOP-16
SOP-16
SOP-16
Packing
Tube
Tape Reel
Tube
Tape Reel
www.unisonic.com.tw
Copyright © 2010 Unisonic Technologies Co., LTD
1 of 6
QW-R502-013.D
4052
PIN CONFIGURATION
CMOS IC
PIN DESCRIPTION
PIN No.
SYMBAL
NAME AND FUNCTION
13, 3
X,Y
Commons Input/Output
6
INH
Inhibit Input
7
V
EE
Supply Voltage
8
V
SS
Ground
10,9
A,B
Binary Control Inputs
12,14,15,11
X0~X3
X Channel Inputs/Outputs
1,5,2,4
Y0~Y3
Y Channel Inputs/Outputs
16
V
DD
Positive Supply Voltage
Note: Control Inputs referenced to V
SS.
Analog Inputs and Outputs reference to V
EE.
V
EE
must be
＜V
SS.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
2 of 6
QW-R502-013.D
4052
ABSOLUTE MAXIMUM RATING
PARAMETER
DC Supply Voltage (Referenced to V
EE
, V
SS
≧V
EE
)
SYMBOL
V
DD
RATINGS
-0.5 ~ +18
CMOS IC
UNIT
V
Input or Output Voltage (DC or Transient)
V
IN
, V
OUT
-0.5 ~ V
DD
+0.5
V
(Referenced to V
SS
for Control Inputs and V
EE
for Switch I/O)
Input Current (DC or Transient), per Control Pin
I
IN
±10
mA
Switch Through Current
I
SW
±25
mA
Power Dissipation
700
mW
P
D
Derating above 65°C
7
mW/°C
Junction Temperature
T
J
125
°C
Operating Temperature Range
T
OPR
-40 ~ +125
°C
Storage Temperature Range
T
STG
-40 ~ +150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
ELECTRICAL CHARACTERISTICS
(Ta=25°C, unless otherwise specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
SUPPLY REQUIREMENTS (Voltages Referenced to V
EE
)
V
DD
– 3≧V
SS
≧V
EE
Power Supply Voltage Range
V
DD
Quiescent Current per
Package
MIN
3
TYP
MAX UNIT
V
µA
µA
µA
µA
µA
µA
V
PP
mV
µV
Ω
Ω
Ω
Ω
Ω
Ω
nA
pF
pF
pF
V
V
V
V
V
V
µA
pF
V
DD
=5V
Control Inputs: V
IN
= V
SS
or V
DD
Switch I/O: V
EE
≦V
I/O
≦V
DD
, and
I
Q
V
DD
=10V
ΔVsw≦500mV(Note
2)
V
DD
=15V
V
DD
=5V
T
a
=25°C only (The channel
Total Supply Current
(Dynamic Plus Quiescent,
I
D(AV)
component, (V
IN
-V
OUT
)/R
ON
, is
V
DD
=10V
excluded.)
Per Package)
V
DD
=15V
SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to V
EE
)
Recommended Peak to Peak Voltage
V
I/O
Channel On or Off
0
Into or Out of the Switch
Recommended Static or Dynamic
ΔVsw
Channel On
0
Voltage Across the Switch (Note2)
Output Offset Voltage
V
O(OFF)
V
IN
= 0V, No Load
ΔVsw≦500mV
(Note2)
V
DD
=5V
ON Resistance
V
IN
= V
IL
or V
IH
(Control), and
R
ON
V
DD
=10V
V
IN
= 0 to V
DD
(Switch)
V
DD
=15V
ΔON
Resistance Between V
DD
=5V
Any Two Channels in the
V
DD
=10V
ΔR
ON
Same Package
V
DD
=15V
V
IN
= V
IL
or V
IH
(Control) Channel to
Channel or Any One Channel,
Off Channel Leakage Current
I
OFF
V
DD
=15V
Capacitance, Switch I/O
C
I/O
Inhibit = V
DD
Capacitance, Common O/I
C
O/I
Inhibit = V
DD
Pins Not Adjacent
Capacitance, Feedthrough
C
I/O
Pins Adjacent
(Channel Off)
CONTROL INPUTS – INHIBIT A, B, C (Voltages Referenced to V
SS
)
V
DD
=5V
V
IL
Low Level Input Voltage
R
ON
= per spec, I
OFF
= per spec
V
DD
=10V
V
DD
=15V
V
DD
=5V
3.5
V
IH
High Level Input Voltage
R
ON
= per spec, I
OFF
= per spec
V
DD
=10V
7.0
V
DD
=15V
11
Input Leakage Current
I
LEAK
V
IN
= 0 or V
DD
, V
DD
=15V
Input Capacitance
C
IN
18
0.005
5
0.010
10
0.015
20
(0.07 µA/kHz) f + I
Q
(0.20 µA/kHz) f + I
Q
(0.36 µA/kHz) f + I
Q
V
DD
600
10
250
120
80
25
10
10
±0.05
10
17
0.15
0.47
2.25
1.5
4.50
3.0
6.75
4.0
2.75
5.50
8.25
±0.00001 ±0.1
5.0
7.5
1050
500
280
70
50
45
±100
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
3 of 6
QW-R502-013.D
4052
DYNAMIC ELECTRICAL CHARACTERISTICS
(C
L
= 50pF, T
a
=25°C, V
EE
≦V
SS
, unless otherwise specified)
PARAMETER
Propagation Delay Times
Switch Input to Switch
Output (R
L
= 10 kΩ)
Inhibit to Output
SYMBOL
t
PLH,
t
PHL
t
PHZ,
t
PLZ
t
PZH,
t
PZL
V
DD
–V
EE
TEST CONDITIONS
Vdc
t
PLH
, t
PHL
=(0.17 ns/pF)C
L
+ 21.5ns
5
t
PLH
, t
PHL
=(0.08 ns/pF)C
L
+ 8.0ns
10
15
t
PLH
, t
PHL
=(0.06 ns/pF)C
L
+ 7.0ns
5
10
15
5
10
15
10
(R
L
=10kΩ, V
EE
=V
SS
)
Output “1” or “0” to High Impedance,
or High Impedance to “1” or “0” Level
R
L
= 10 kΩ, V
EE
= V
SS
MIN
TYP
30
12
10
300
155
125
325
130
90
0.07
CMOS IC
MAX
75
30
25
600
310
250
650
260
180
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Control Input to Output
Total Harmonic Distortion
t
PLH,
t
PHL
THD
R
L
= 10KΩ, f = 1 kHz, V
IN
= 5 V
PP
R
L
= 1kΩ, V
IN
= 1/2 (V
DD
–V
EE
) p–p,
Bandwidth
BW
10
17
MHz
C
L
= 50pF, 20 Log (V
OUT
/V
IN
) = -3dB)
R
L
=1KΩ, V
IN
= 1/2 (V
DD
–V
EE
) p–p
Off Channel Feedthrough
10
-50
dB
Attenuation
f
IN
= 30MHz
R
L
= 1kΩ, V
IN
= 1/2 (V
DD
–V
EE
) p–p
Channel Separation
10
-50
dB
f
IN
= 3MHz
Crosstalk, Control Input to
R
1
= 1kΩ, R
L
= 10kΩ Control
10
75
mV
Common O/I
t
TLH
= t
THL
= 20ns, Inhibit = V
SS
Note: 1. Data of “TYP” is intended as an indication of the IC’s potential performance.
2. For voltage drops across the switch(ΔVsw)>600mV (>300mV at high temperature), excessive V
DD
current
may be drawn, i.e. the current out of the switch may contain both V
DD
and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
4 of 6
QW-R502-013.D
4052
TEST CIRCUIT
CMOS IC
V
DD
IN/OUT
V
DD
V
DD
OUT/IN
V
EE
V
DD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
V
EE
CONTROL
Switch Circuit Schematic
TRUTH TABLE
16
INH
A
B
ON Switches
X0
X0
Y0
X1
Y1
X2
Y2
X3
Y3
None
X1
X2
X3
Y0
Y1
Y2
Y3
12
14
15
11
1
5
2
4
UTC 4052 Functional Diagram
3 Y
13 X
6
10
9
LEVEL
CONVERTER
8
Vss 7
V
EE
V
DD
BINARY TO 1-OF-4
DECODER WITH
INHIBIT
TRUTH TABLE
Control Inputs
Select
Inhibit
0
0
0
0
1
B
0
0
1
1
X
A
0
1
0
1
X
* X=Don't Care
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
5 of 6
QW-R502-013.D
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
