March 1996
NDC7001C
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N and P-channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process has been designed to minimize on-state resistance,
provide rugged and reliable performance and fast switching.
These devices is particularly suited for low voltage, low
current, switching, and power supply applications.
Features
N-Channel 0.51A, 50V, R
DS(ON)
= 2
Ω
@ V
GS
=10V
P-Channel -0.34A, -50V. R
DS(ON)
= 5
Ω
@ V
GS
=-10V.
High density cell design for low R
DS(ON)
.
Proprietary SuperSOT
TM
-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High saturation current.
____________________________________________________________________________________________
4
3
5
2
6
SuperSOT
TM
-6
1
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
N-Channel
50
20
(Note 1a)
P-Channel
-50
-20
-0.34
-1
0.96
0.9
0.7
-55 to 150
Units
V
V
A
Gate-Source Voltage - Continuous
Drain Current - Continuous
- Pulsed
0.51
1.5
P
D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
130
60
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDC7001C.SAM
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Type
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, I
D
= -250 µA
Zero Gate Voltage Drain Current
V
DS
= 40 V, V
GS
= 0 V
T
J
= 125°C
V
DS
= -40 V, V
GS
= 0 V
T
J
= 125°C
I
GSSF
I
GSSR
V
GS(th)
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
J
= 125°C
V
DS
= V
GS
, I
D
= -250 µ.A
T
J
= 125°C
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 10 V, I
D
= 0.51 A
T
J
= 125°C
V
GS
= 4.5 V, I
D
= 0.35 A
V
GS
= -10 V, I
D
= -0.34 A
T
J
= 125°C
V
GS
= -4.5 V, I
D
= -0.25 A
I
D(on)
g
FS
On-State Drain Current
V
GS
= 10 V, V
DS
= 10 V
V
GS
= -10 V, V
DS
= -10 V
Forward Transconductance
V
DS
= 10 V, I
D
= 0.51 A
V
DS
= -10 V, I
D
= -0.34 A
DYNAMIC CHARACTERISTICS
N-Ch
P-Ch
N-Ch
P-Ch
1.5
-1
400
250
mS
P-Ch
N-Ch
P-Ch
All
All
P-Ch
N-Ch
P-Ch
N-Ch
50
-50
1
500
-1
-500
100
-100
nA
nA
µA
V
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
N-Ch
1
0.8
-1
-0.8
1.9
1.5
-2.5
-2.2
1
1.7
1.6
2.5
4
5.3
2.5
2.2
-3.5
-3
2
3.5
4
5
10
7.5
A
V
Ω
C
iss
C
oss
C
rss
Input Capacitance
N-Channel
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
P-Channel
V
DS
= -25 V, V
GS
= 0 V,
f = 1.0 MHz
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
20
40
13
13
5
4
pF
Output Capacitance
Reverse Transfer Capacitance
pF
pF
NDC7001C.SAM
Electrical Characteristics
(T
A
= 25
o
C unless otherwise noted)
Symbol
Parameters
Conditions
Type
Min
Typ
Max
Units
SWITCHING CHARACTERISTICS
(Note 2)
t
D(on)
Turn - On Delay Time
Turn - On Rise Time
N-Channel
V
DD
= 25 V, I
D
= 0.25 A,
V
GS
= 10 V, R
GEN
= 25
Ω
P-Channel
V
DD
= -25 V, I
D
= -0.25 A,
V
GS
= -10 V, R
GEN
= 25
Ω
N-Ch
P-Ch
N-Ch
P-Ch
t
D(off)
Turn - Off Delay Time
N-Ch
P-Ch
N-Ch
P-Ch
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
N-Channel
V
DS
= 25 V,
I
D
= 0.51 A, V
GS
= 10 V
P-Channel
V
DS
= -25 V,
I
D
= -0.34 A, V
GS
= -10 V
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
I
SM
V
SD
Maximum Continuous Source Current
N-Ch
P-Ch
Maximum Pulse Source Current
(Note 2)
Drain-Source Diode Forward Voltage
N-Ch
P-Ch
V
GS
= 0 V, I
S
= 0.51 A
(Note 2)
V
GS
= 0 V, I
S
= -0.34 A
(Note 2)
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
6
14
6
6
11
13
5
6
1
1.3
0.19
0.23
0.33
0.38
20
20
20
20
20
20
20
20
nS
t
r
t
f
Turn - Off Fall Time
nC
nC
Gate-Drain Charge
nC
0.51
-0.34
1.5
-1
0.8
-0.8
1.2
-1.2
A
A
V
N-Ch
P-Ch
P
D
(
t
) =
R
θ
JA
(
t
)
T
J
−
T
A
=
R
θ
JC
+
R
θ
CA
(
t
)
T
J
−
T
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 130
o
C/W when mounted on a 0.125 in
2
pad of 2oz cpper.
b. 140 C/W when mounted on a 0.005 in pad of 2oz cpper.
c. 180
o
C/W when mounted on a 0.0015 in
2
pad of 2oz cpper.
o
2
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDC7001C.SAM
Typical Electrical Characteristics: N-Channel
1.5
3
V
GS
=10V
I
D
, DRAIN-SOURCE CURRENT (A)
1.2
8.0 7.0
DRAIN-SOURCE ON-RESISTANCE
6.0
5.5
R
DS(on)
, NORMALIZED
V
GS
= 3.5V
2.5
4.0
4.5
5.0
5.0
0.9
2
5.5
6.0
7.0
8.0
10
4.5
0.6
1.5
4.0
0.3
1
3.5
3.0
0.5
0
0.3
0
0
1
V
DS
2
3
4
, DRAIN-SOURCE VOLTAGE (V)
5
0.6
0.9
I
D
, DRAIN CURRENT (A)
1.2
1.5
Figure 1. N-Channel On-Region Characteristics.
Figure 2. N-Channel On-Resistance Variation with
Gate Voltage and Drain Current.
2
1.8
DRAIN-SOURCE ON-RESISTANCE
R
DS(ON)
NORMALIZED
,
1.6
1.4
1.2
1
0.8
0.6
0.4
-50
2.5
V
GS
= 10V
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I
D
= 0.51A
V
GS
= 10V
2
TJ = 125°C
1.5
25°C
1
-55°C
0.5
0
0.3
I
D
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
0.6
0.9
, DRAIN CURRENT (A)
1.2
1.5
Figure 3. N-Channel On-Resistance Variation with
Temperature.
Figure 4. N-Channel On-Resistance Variation with
Drain Current and Temperature.
1.5
1.2
25°C
125°C
V
th
, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
V
DS
= 10V
1.2
I
D
, DRAIN CURRENT (A)
T
J
= -55°C
1.1
V
DS
= V
GS
I
D
= 250µA
0.9
1
0.6
0.9
0.3
0.8
0
1
2
3
4
5
6
V
GS
, GATE TO SOURCE VOLTAGE (V)
7
8
0.7
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. N-Channel Transfer Characteristics.
Figure 6. N-Channel Gate Threshold Variation
with Temperature.
NDC7001C.SAM
Typical Electrical Characteristics: N-Channel
(continued)
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.16
I
D
= 250µA
I
S
, REVERSE DRAIN CURRENT (A)
1.5
1
0.5
V
GS
= 0V
1.12
1.08
1.04
1
0.96
0.92
0.88
-50
BV
DSS
, NORMALIZED
TJ = 125°C
0.1
25°C
-55°C
0.01
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.001
0.2
0.4
0.6
0.8
1
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 7. N-Channel Breakdown Voltage Variation
with Temperature.
Figure 8. N-Channel Body Diode Forward Voltage
Variation with Current and Temperature
.
100
50
10
V
DS
= 25V
V
GS
, GATE-SOURCE VOLTAGE (V)
8
I
D
= 0.51A
CAPACITANCE (pF)
C iss
20
10
6
C oss
C rss
f = 1 MHz
4
5
2
2
1
0.1
V
GS
= 0 V
0.2
0.5
1
2
5
10
20
50
0
0
0.2
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0.4
0.6
0.8
Q
g
, GATE CHARGE (nC)
1
1.2
Figure 9. N-Channel Capacitance Characteristics.
Figure 10. N-Channel Gate Charge Characteristics.
0.7
V
DS
= 10V
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.3
V
GS
TJ = -55°C
25°C
I
D
, DRAIN CURRENT (A)
125°C
0.6
0.9
1.2
, GATE TO SOURCE VOLTAGE (V)
1.5
Figure 11. N-Channel Transconductance Variation
with Drain Current and Temperature.
NDC7001C.SAM
stm32/stm8
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