MIC5821/5822
Micrel, Inc.
MIC5821/5822
8-Bit Serial-Input Latched Drivers
Final Information
General Description
BiCMOS technology gives the MIC5821/5822 family flexibil-
ity beyond the reach of standard logic buffers and power
driver arrays. These devices each have an eight-bit CMOS
shift register, CMOS control circuitry, eight CMOS data
latches, and eight bipolar current-sink Darlington output
drivers. The 500mA outputs are suitable for use with incan-
descent bulbs and other moderate to high current loads. The
drivers can be operated with a split supply where the negative
supply is down to –20V. Except for maximum driver output
voltage ratings, the MIC5821 and MIC5822 are identical.
These devices have greatly improved data-input rates. With
a 5V logic supply they will typically operate faster than 5
MHz. With a 12V supply significantly higher speeds are
obtained. The CMOS inputs are compatible with standard
CMOS, PMOS, and NMOS logic levels. TTL and DTL circuits
may require the use of appropriate pull-up resistors. By using
the serial data output, the drivers can be cascaded for
interface applications requiring additional drive lines.
Features
•
•
•
•
•
•
3.3 MHz Minimum Data-Input Rate
CMOS, PMOS, NMOS, TTL Compatible
Internal Pull-Down or Pull-Up Resistors
Low-Power CMOS Logic and Latches
High-Voltage Current-Sink Outputs
Single or Split Supply Operation
Ordering Information
Part Number
Standard
Pb-Free
MIC5821BN
MIC5822BN
MIC5821YN
MIC5822YN
Temp Range
–40°C to +85°C
–40°C to +85°C
Package
16-Pin Plastic DIP
16-Pin Plastic DIP
Functional Diagram
CLK
1
Pin Configuration
CLOCK
5
8-BIT SERIAL-PARALLEL SHIFT REGISTER
1
16
15
14
LATCHES
SERIAL
DATA IN
SERIAL
DATA OUT
V
DD
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
SERIAL DATA IN 2
V SS
VDD
SERIAL DATA OUT
3
4
5
6
7
8
SUB
2
4
SHIFT REGISTER
V
SS
3
LATCHES
6
STROBE
13
12
11
10
9
7
MOS
Bipolar
OUTPUT ENABLE
(ACTIVE LOW)
STROBE
OUTPUT ENABLE
Sub
8
16
15
14
13
12
11
10
9
GND
V
EE
VEE
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
(Plastic DIP)
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
February 2005
1
MIC5821/5822
MIC5821/5822
Micrel, Inc.
Typical Input Circuits
Absolute Maximum Ratings (Note 1)
at 25°C Free-Air Temperature and V
SS
= 0V
(MIC5821)
50V
(MIC5822)
80V
Output Voltage, V
CE SUS
(MIC5821)(Note 3)
35V
(MIC5822)(Note 3)
50V
Logic Supply Voltage, V
DD
15V
Input Voltage Range, V
IN
–0.3V to V
DD
+ 0.3V
V
DD
– V
EE
25V
Emitter Supply Voltage, V
EE
–20V
Continuous Output Current, I
OUT
500mA
Package Power Dissipation, P
D(Note 1)
1.67W
Operating Temperature Range, T
A
–55°C to +85°C
Storage Temperature Range, T
S
–65°C to +150°C
Output Voltage, V
CE
Note 1: Derate at the rate of 16.7mW/°C above T
A
= 25°C.
Note 2: CMOS devices have input static protection but are susceptible to
damage when exposed to extremely high static electrical
charges.
Note 3: For inductive load applications.
Note 4: Specification for packaged product only.
V
DD
STROBE
OUTPUT
ENABLE
V
SS
V
DD
Typical Output Driver
CLOCK
SERIAL
DATA IN
OUT
N
7.2k
3k
SUB
V
EE
V
SS
Maximum Allowable Duty Cycle (Plastic DIP)
Number of Outputs ON
(I
OUT
= 200mA
V
DD
= 12V)
8
7
6
5
4
3
2
1
Maximum Allowable Duty Cycle at Ambient Temperature of
25
°
C
73%
83%
97%
100%
100%
100%
100%
100%
40
°
C
62%
71%
82%
98%
100%
100%
100%
100%
50
°
C
55%
62%
72%
87%
100%
100%
100%
100%
60
°
C
47%
54%
63%
75%
93%
100%
100%
100%
70
°
C
40%
46%
53%
63%
79%
100%
100%
100%
MIC5821/5822
2
February 2005
MIC5821/5822
Micrel, Inc.
Electrical Characteristics
(Note 4)
at T
A
= 25°C V
DD
= 5V, V
EE
= V
SS
= 0V (unless otherwise specified)
Applicable
Characteristic
Output Leakage Current
Symbol
I
CEX
Devices
MIC5821
MIC5822
Collector-Emitter
Saturation Voltage
Input Voltage
V
IN(0)
V
IN(1)
Both
Both
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
Input Resistance
R
IN
Both
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
Supply Current
I
DD(ON)
Both
One Driver ON, V
DD
= 12V
One Driver ON, V
DD
= 10V
One Driver ON, V
DD
= 5.0V
All Drivers ON, V
DD
= 12V
All Drivers ON, V
DD
= 10V
All Drivers ON, V
DD
= 5.0V
I
DD(OFF)
Both
All Drivers OFF, V
DD
= 5.0V,
All Inputs = 0V
All Drivers OFF, V
DD
= 12V,
All Inputs= 0V
10.5
8.5
3.5
50
50
50
4.5
3.9
2.4
16
14
8
1.6
2.9
mA
kΩ
V
CE(SAT)
Both
Test Conditions
V
OUT
= 50V
V
OUT
= 50V, T
A
= +70°C
V
OUT
= 80V
V
OUT
= 80V, T
A
= +70°C
I
OUT
= 100mA
I
OUT
= 200mA
I
OUT
= 350mA, V
DD
= 7.0V
Min.
Limits
Max.
50
100
50
100
1.1
1.3
1.6
0.8
V
V
Unit
µA
Electrical Characteristics
(Note 4)
Characteristic
Output Leakage Current
Collector-Emitter
Saturation Voltage
Input Voltage
V
IN0)
V
IN(1)
Input Resistance
RIN
Symbol
I
CEX
V
CE(SAT)
T
A
= –55°C, V
DD
= 5V, V
SS
= V
EE
= 0V (unless otherwise noted)
Limits
Test Conditions
V
OUT
= 80V
I
OUT
= 100mA
I
OUT
= 200mA
I
OUT
= 350mA, V
DD
= 7.0V
V
DD
= 12V
V
DD
= 5.0V
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
10.5
3.5
35
35
35
5.5
4.5
3.0
16
14
10
3.5
2.0
mA
kΩ
Min.
Max.
50
1.3
1.5
1.8
0.8
V
Unit
µA
V
Supply Current
I
DD(ON)
One Driver ON, V
DD
= 12V
One Driver ON, V
DD
= 10V
One Driver ON, V
DD
= 5.0V
All Drivers ON, V
DD
= 12V
All Drivers ON, V
DD
= 10V
All Drivers ON, V
DD
= 5.0V
I
DD(OFF)
All Drivers OFF, V
DD
= 12V
All Drivers OFF, V
DD
= 5.0V
February 2005
3
MIC5821/5822
MIC5821/5822
Micrel, Inc.
Electrical Characteristics
(Note 4)
T
A
= +125°C, V
DD
= 5V, V
SS
= V
EE
= 0V (unless otherwise noted)
Limits
Characteristic
Output Leakage Current
Collector-Emitter
Saturation Voltage
Input Voltage
V
IN(0)
V
IN(1)
Input Resistance
R
IN
V
DD
= 12V
V
DD
= 5.0V
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
Supply Current
I
DD(ON)
One Driver ON, V
DD
= 12V
One Driver ON, V
DD
= 10V
One Driver ON, V
DD
= 5.0V
All Drivers ON, V
DD
= 12V
All Drivers ON, V
DD
= 10V
All Drivers ON, V
DD
= 5.0V
I
DD(OFF)
All Drivers OFF, V
DD
= 12V
All Drivers OFF, V
DD
= 5.0V
10.5
3.5
50
50
50
4.5
3.9
2.4
16
14
8
2.9
1.6
mA
kΩ
Symbol
I
CEX
V
CE(SAT)
Test Conditions
V
OUT
= 80V
I
OUT
= 100mA
I
OUT
= 200mA
I
OUT
= 350mA, V
DD
= 7.0V
Min.
Max.
500
1.3
1.5
1.8
0.8
V
Unit
µA
V
MIC5821/5822 Family Truth Table
Serial
Data
Input
H
L
X
Clock
Input
Shift Register Contents
I
1
H
L
R
1
X
P
1
I
2
R
1
R
1
R
2
X
P
2
I
3
……
I
8
Serial
Data Strobe
Output Input
R
7
R
7
R
8
X
P
8
L
H
R
1
P
1
X
L = Low Logic Level H = High Logic Level
X = Irrelevant
Latch Contents
I
1
I
2
I
3
……
I
8
Output
Enable
I
1
Output Contents
I
2
I
3
……
I
8
R
2
…… R
7
R
2
…… R
7
R
3
…… R
8
X …… X
P
3
…… P
8
R
2
P
2
X
R
3
…… R
8
P
3
…… P
8
X
……
X
L
H
P
1
H
P
2
H
P
3
…… P
8
H
……
H
P = Present State R = Previous State
Timing Diagram
CLOCK
A
B
DATA IN
E
STROBE
OUTPUT
ENABLE
OUT
N
C
F
D
G
MIC5821/5822
4
February 2005
MIC5821/5822
Micrel, Inc.
Timing Conditions
(T
A
= +25°C, Logic Levels are V
DD
and V
SS
)
V
DD
= 5.0V
A.
B.
C.
D.
E.
F.
G.
Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) ....................................................................... 75 ns
Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................. 75 ns
Minimum Data Pulse Width .................................................................................................................................... 150 ns
Minimum Clock Pulse Width ................................................................................................................................... 150 ns
Minimum Time Between Clock Activation and Strobe ............................................................................................ 300 ns
Minimum Strobe Pulse Width .................................................................................................................................. 100 ns
Typical Time Between Strobe Activation and Output Transition ............................................................................. 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).
The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed
(STROBE tied high) will require that the ENABLE input be high during serial entry.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting the information stored in the
latches or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches.
Typical Applications
MIC5822 Level Shifting Lamp Driver with Darlington Emitters Tied to a Negative Supply
SERIAL DATA CLOCK
-9V
1
2
SHIFT REGISTER
16
15
14
LATCHES
3
+5V
4
5
6
0.1µ
7
8
SUB
13
12
11
10
9
+
100µ
February 2005
5
MIC5821/5822
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