REI Datasheet
SN54ALS878A, SN54ALS879A, SN54AS878, SN54AS879
SN74ALS878A, SN74ALS879A, SN74AS878, SN74AS879
Dual 4-Bit D-Type Edge-Triggered Flip-Flops with 3-State Outputs
These dual 4-bit registers feature 3-state outputs designed specifically for bus driving. This makes
these devices particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The dual 4-bit edge-triggered flip-flops enter data on the low-to-high transition of the clock (1CLK and
2CLK). All types have individual synchronous clear inputs and output control pins for each group of
4-bit registers.
Rochester Electronics
Manufactured Components
Rochester branded components are
manufactured using either die/wafers
purchased from the original suppliers
or Rochester wafers recreated from the
original IP. All recreations are done with
the approval of the OCM.
Parts are tested using original factory
test programs or Rochester developed
test solutions to guarantee product
meets or exceeds the OCM data sheet.
Quality Overview
• ISO-9001
• AS9120 certification
• Qualified Manufacturers List (QML) MIL-PRF-38535
• Class Q Military
• Class V Space Level
• Qualified Suppliers List of Distributors (QSLD)
• Rochester is a critical supplier to DLA and
meets all industry and DLA standards.
Rochester Electronics, LLC is committed to supplying
products that satisfy customer expectations for
quality and are equal to those originally supplied by
industry manufacturers.
The original manufacturer’s datasheet accompanying this document reflects the performance
and specifications of the Rochester manufactured version of this device. Rochester Electronics
guarantees the performance of its semiconductor products to the original OEM specifications.
‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be
based on product characterization, design, simulation, or sample testing.
© 2013 Rochester Electronics, LLC. All Rights Reserved 12232013
To learn more, please visit
www.rocelec.com
SN54ALS878A, SN54ALS879A, SN54AS878, SN54AS879
SN74ALS878A, SN74ALS879A, SN74AS878, SN74AS879
DUAL 4 BIT D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS
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•
•
•
•
•
3-State Bus Driving Outputs
Full Parallel-Access for Loading
Buffered Control Inputs
Choice of True or Inverting Logic
’ALS878A, ’AS878 True Outputs
’ALS879A, ’AS879 Inverting Outputs
Synchronous Clear
Package Options Include Plastic Small
Outline Packages, Both Plastic and
Ceramic Chip Carriers, and Standard
Plastic and Ceramic 300-mil DIPs
Dependable Texas Instruments Quality and
Reliability
SN54ALS878A, SN54AS878 . . . JT PACKAGE
SN74ALS878A, SN74AS878 . . . DW OR NT PACKAGE
(TOP VIEW)
1CLR
1OC
1D1
1D2
1D3
1D4
2D1
2D2
2D3
2D4
2OC
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
1CLK
1Q1
1Q2
1Q3
1Q4
2Q1
2Q2
2Q3
2Q4
2CLK
2CLR
SDAS062A − D2661, APRIL 1982 − REVISED MAY 1986
SN54ALS878A, SN54AS878 . . . FK PACKAGE
SN74ALS878A, SN74AS878 . . . FN PACKAGE
(TOP VIEW)
1D1
1OC
1CLR
NC
VCC
1CLK
1Q1
1D2
1D3
1D4
NC
2D1
2D2
2D3
4 3 2 1 28 27 26
25
5
6
24
7
23
8
22
9
21
10
20
11
19
121314
15
16 1718
description
These dual 4-bit registers feature 3-state outputs
designed specifically for bus driving. This makes
these devices particularly suitable for implement-
ing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The dual 4-bit edge-triggered flip-flops enter data
on the low-to-high transition of the clock (1CLK
and 2CLK). All types have individual synchronous
clear inputs and output control pins for each group
of 4-bit registers.
The SN54ALS’ and SN54AS’ devices are
characterized for operation over the full military
temperature range of − 55°C to 125°C. The
SN74ALS’ and SN74AS’ devices are character-
ized for operation from 0°C to 70°C.
1Q2
1Q3
1Q4
NC
2Q1
Q22
2Q3
SN54ALS879A, SN54AS879 . . . JT PACKAGE
SN74ALS879A, SN74AS879 . . . DW OR NT PACKAGE
(TOP VIEW)
1CLR 1 24 VCC
1OC 2 23 1CLK
1D1 3 22 1Q1
1D2 4 21 1Q2
1D3 5 20 1Q3
1D4 6 19 1Q4
2D1 7 18 2Q1
2D2 8 17 2Q2
2D3 9 16 2Q3
2D4 10 15 2Q4
2OC 11 14 2CLK
GND 12 13 2CLR
SN54ALS879A, SN54AS879 . . . FK PACKAGE
SN74ALS879A, SN74AS879 . . . FN PACKAGE
(TOP VIEW)
1D1
1OC
1CLR
NC
VCC
1CLK
1Q1
1D2
1D3
1D4
NC
2D1
2D2
2D3
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
121314
15
16 17 18
2D4
2OC
GND
NC
2CLR
2CLK
2Q4
1Q2
1Q3
1Q4
NC
2Q1
2Q2
2Q3
NC − No internal connection
Copyright
1986, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
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•
2D4
2OC
GND
NC
2CLR
2CLK
2G4
1
SDAS062A − D2661, APRIL 1982 − REVISED MAY 1986
SN54ALS878A, SN54ALS879A, SN54AS878, SN54AS879
SN74ALS878A, SN74ALS879A, SN74AS878, SN74AS879
DUAL 4 BIT D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS
FUNCTION TABLES
’ALS878A, ’AS878
(each flip-flop)
INPUTS
OC
L
L
L
L
H
CLR CLK
L
H
H
H
X
↑
↑
↑
L
X
D
X
H
L
X
X
OUTPUT
Q
L
H
L
Q0
Z
OC
L
L
L
L
H
’ALS879A, ’AS879
(each flip-flop)
INPUTS
CLR CLK
L
H
H
H
X
↑
↑
↑
L
X
D
X
H
L
X
X
OUTPUT
Q
H
L
H
Q0
Z
logic symbols
†
’ALS878A, ’AS878
2
1OC
23
1CLK
1
1CLR
3
1D1
4
1D2
5
1D3
6
1D4
11
2OC
14
2CLK
13
2CLR
7
2D1
8
2D2
9
2D3
10
2D4
EN
C1
1R
1D
22
21
20
19
1Q1
1Q2
1Q3
1Q4
2
1OC
23
1CLK
1
1CLR
3
1D1
4
1D2
5
1D3
6
1D4
11
2OC
14
2CLK
13
2CLR
18
17
16
15
2Q1
2Q2
2Q3
2Q4
7
2D1
8
2D2
9
2D3
10
2D4
’ALS879A, ’AS879
EN
C1
1R
1D
22
21
20
19
1Q1
1Q2
1Q3
1Q4
EN
C1
1R
1D
EN
C1
1R
1D
18
17
16
15
2Q1
2Q2
2Q3
2Q4
† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for DW, JT, and NT packages.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
•
•
SN54ALS878A, SN54ALS879A
SN74ALS878A, SN74ALS879A
DUAL 4 BIT D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS
SDAS062A − D2661, APRIL 1982 − REVISED MAY 1986
logic diagrams (positive logic)
’ALS878A, ’AS878
(each quad flip-flop)
OC
CLK
CLR
Q1
D1
C1
1D
D1
C1
1D
OC
CLK
CLR
Q1
’ALS879A, ’AS879
(each quad flip-flop)
Q2
D2
C1
1D
D2
C1
1D
Q2
Q3
D3
C1
1D
D3
C1
1D
Q3
Q4
D4
C1
1D
D4
C1
1D
Q4
Pin numbers shown are for DW, JT, and NT packages.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
•
•
3
SDAS062A − D2661, APRIL 1982 − REVISED MAY 1986
SN54ALS878A, SN54ALS879A
SN74ALS878A, SN74ALS879A
DUAL 4 BIT D TYPE EDGE TRIGGERED FLIP FLOPS WITH 3 STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54ALS878A, SN54ALS879A . . . . . . . . . . . . . . . . −55°C to 125°C
SN74ALS878A, SN74ALS879A . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
recommended operating conditions
SN54ALS878A
SN54ALS879A
MIN
VCC
VIH
VIL
IOH
IOL
fclock
tw
tsu
th
TA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
Pulse duration
Setup time before CLK↑
Hold time after CLK↑
’ALS878A
’ALS879A
’ALS878A CLK high or low
’ALS879A CLK high or low
Data
CLR
Data
CLR
0
0
20
25
15
20
4
0
−55
125
4.5
2
0.7
−1
12
25
20
0
0
16.5
20
15
20
4
0
0
70°
NOM
5
MAX
5.5
SN74ALS878A
SN74ALS879A
MIN
4.5
2
0.8
−2.6
24
30
25
NOM
5
MAX
5.5
V
V
V
mA
mA
MHz
ns
ns
ns
°C
UNIT
Operating free-air temperature
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS878A
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V
II = − 18 mA
IOH = − 0.4 mA
IOH = − 1 mA
IOH = − 2.6 mA
IOL = 12 mA
IOL = 24 mA
VO = 2. 7 V
VO = 0.4 V
VI = 7 V
VO = 2.7 V
VI = 0 .4 V
VO = 2.25 V
Outputs high
ICC
Outputs low
Outputs disabled
−30
14
18
20
SN54ALS879A
MIN TYP
†
MAX
−1.2
VCC −2
2.4
VCC −2
3.3
2.4
0.25
0.4
20
−20
0.1
20
−0.2
−112
23
31
33
−30
14
18
20
3.2
0.25
0.35
0.4
0.5
20
−20
0.1
20
−0.2
−112
23
31
33
mA
V
µA
µA
mA
µA
mA
mA
V
SN74ALS878A
SN74ALS879A
MIN TYP
†
MAX
−1.2
UNIT
V
VOL
IOZH
IOZL
II
IIH
IIL
IO‡
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
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•
FPGA/CPLD
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