DATASHEET
VCXO AND SET-TOP CLOCK SOURCE
Description
The MK2771-16 is a low-cost, low-jitter, high-performance
VCXO and clock synthesizer designed for set-top boxes.
The on-chip Voltage Controlled Crystal Oscillator accepts a
0 to 3 V input voltage to cause the output clocks to vary by
±100 ppm. Using IDT’s patented VCXO and analog
Phase-Locked Loop (PLL) techniques, the device uses an
inexpensive 13.5 MHz pullable crystal input to produce
multiple output clocks including two selectable processor
clocks, a selectable audio clock, two communications
clocks, a 13.5 MHz clock, and three 27 MHz clocks. All
clocks are frequency locked to the 27 MHz output (and to
each other) with zero ppm error, so any output can be used
as the VCXO output.
MK2771-16
Features
•
Packaged in 28-pin QSOP
•
Available in RoHS 5 (green) or RoHS 6 (green and lead
free) compliant package
•
On-chip patented VCXO with pull range of 200 ppm
•
VCXO tuning voltage of 0 to 3 V
•
Processor frequencies include 16.66, 20, 25, 32, 40, and
•
•
•
•
•
•
50 MHz
Audio clocks support 32 kHz, 44.1 kHz, 48 kHz, and 96
kHz sampling rates
Zero ppm synthesis error in all clocks (all exactly track 27
MHz VCXO)
Uses an inexpensive 13.5 MHz pullable crystal
Full CMOS output swings with 25 mA output drive
capability at TTL levels
Advanced, low-power, sub-micron CMOS process
5 V operating voltage with 3.3 V capable I/O
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
VDD5
3
ACLK
3
2
2
PLL Clock
Synthesis
Circuitry
PCLK
CCLK1
CCLK2
VDDIO
AS2:0
PS1, PS0
CS1, CS0
VIN
X1
X2
13.5 MHz
pullable
crystal
Voltage
Controlled
Crystal
Oscillator
x2
PLL
divide
by 2
6
3
27.000 MHz
13.500 MHz
Optional crystal capacitors.
GND
IDT™
VCXO AND SET-TOP CLOCK SOURCE
1
MK2771-16
REV F 122109
MK2771-16
VCXO AND SET-TOP CLOCK SOURCE
VCXO AND SYNTHESIZER
Pin Assignment
PS0
X2
GND
X1
VDD5
VIN
VDDIO
VDD5
CS1
GND
GND
PCLK
CCLK2
ACLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AS1
AS0
CS0
27M
GND
27M
VDD5
AS2
GND
GND
27M
CCLK1
PS1
13.5M
Processor Clock Select Table (MHz)
PS1
PS0
PCLK
0
0
M
M
1
1
0
1
0
1
0
1
50
16.667
25
32
40
20
Audio Clock Table (MHz)
AS2
AS1
AS0
ACLK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8.192
11.2896
12.288
5.6448
18.432
16.9344
49.152
21.576
28-pin QSOP
Communications Clock Table (MHz)
CS1
CS0
CCLK1
CCLK2
0
0
1
1
0
1
0
1
Low
Low
11.0592
11.0592
33.333
24.576
18.432
3.6864
0 = connect directly to ground
1 = connect directly to VDDIO
M = leave floating or unconnected
IDT™
VCXO AND SET-TOP CLOCK SOURCE
2
MK2771-16
REV F 122109
MK2771-16
VCXO AND SET-TOP CLOCK SOURCE
VCXO AND SYNTHESIZER
Pin Descriptions
Pin
Number
1
2
3, 10, 11
4
5, 8, 22
6
7
9
12
13
14
15
16
17
18, 23, 25
19, 20, 24
21
26
27
28
Pin
Name
PS0
X2
GND
X1
VDD5
VIN
VDDIO
CS1
PCLK
CCLK2
ACLK
13.5M
PS1
CCLK1
27M
GND
AS2
CS0
AS0
AS1
Pin Type
Input
Pin Description
Processor clock select 0. Selects PCLK frequency. See table
above. Internal pull-up resistor.
XO
Crystal connection. Connect to a 13.5 MHz fundamental mode
pullable crystal.
Power
Connect to ground.
XI
Crystal connection. Connect to a 13.5 MHz fundamental mode
pullable crystal.
Power
Connect to +5 V.
Input
Voltage input to VCXO. Zero to 3 V signal which controls the
frequency of the VCXO.
Power
Connect to +3.3 V or +5 V. Amplitude of inputs and outputs will
match this.
Input
Communications clock select pin 1. Selects CCLK 1 and 2 per
table above. Internal pull-up.
Output
Processor clock output. Determined by status of PS1, PS0.
Output
Communications clock output 2 determined by status of CS1,
CS0 per table above.
Output
Audio clock output. Determined by status of AS2:0 per table
above.
Output
13.5 MHz VCXO clock output.
Tri-level Input Processor Clock Select 1. Selects PCLK frequency. See table
above. Self-biased to M.
Output
Communications clock output 1 determined by status of CS1,
CS0 per table above.
Output
27 MHz VCXO clock output.
Power
Connect to ground.
Input
Audio clock select 2. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.
Input
Communications clock select pin 0. Selects CCLK 1 and 2 per
table above. Internal pull-up.
Input
Audio clock select 0. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.
Input
Audio clock select 1. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.
IDT™
VCXO AND SET-TOP CLOCK SOURCE
3
MK2771-16
REV F 122109
MK2771-16
VCXO AND SET-TOP CLOCK SOURCE
VCXO AND SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2771-16. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD (referenced to GND)
Inputs and Clock Outputs (referenced to GND)
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125° C
260° C
DC Electrical Characteristics
Unless stated otherwise,
VDD = 5 V ±5%,
Ambient Temperature 0 to +70° C
Parameter
Operating Voltage
Operating Voltage
Input High Voltage, X1 pin only
Input Low Voltage, X1 pin only
Input High Voltage (except
PS1)
Input Low Voltage (except
PS1)
Input High Voltage (PS1 only)
Input Low Voltage (PS1 only)
Output High Voltage
Output Low Voltage
Output High Voltage, CMOS
Level
Operating Supply Current
Operating Supply Current
Short Circuit Current
Input Capacitance, except X1
Frequency Synthesis Error
VIN, VCXO Control Voltage
Symbol
VDD
VDDIO
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD5
IDDIO
I
OS
C
IN
Conditions
All inputs/outputs
Min.
4.75
3.00
3.5
2
Typ.
Max.
5.25
5.25
Units
V
V
V
V
V
2.5
2.5
1.5
0.8
VDD-0.5
0.5
I
OH
= -25 mA
I
OL
= 25 mA
I
OH
= -8 mA
No load, Note 1
No load, VDDIO
= 3.3 V
Each output
Except X1, X2
All clocks
0
2.4
–
VDD-0.4
42
19
±100
7
0
3
–
0.4
V
V
V
V
V
V
mA
mA
mA
pF
ppm
V
IDT™
VCXO AND SET-TOP CLOCK SOURCE
4
MK2771-16
REV F 122109
MK2771-16
VCXO AND SET-TOP CLOCK SOURCE
VCXO AND SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise,
VDD = 5 V±5%,
Ambient Temperature 0 to +70° C
Parameter
Crystal Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Maximum Absolute Jitter,
short term
27 MHz Output Pullability
Symbol
t
OR
t
OF
t
OD
t
ja
Conditions
0.8 to 2.0 V
2.0 to 0.8 V
At 1.4 V
Min.
Typ.
13.5
1.5
1.5
Max.
Units
MHz
ns
ns
40
300
60
%
ps
ppm
0V < VIN < 3 V, Note 3
±100
±140
Note 1: With all clocks at highest frequencies.
Note 2: With a pullable crystal that conforms to IDT’s specifications.
Pullable Crystal Specifications
Frequency
Correlation (load) Capacitance
C0/C1
ESR
Operating Temperature
Initial Accuracy
Temperature plus Aging Stability
13.500000 MHz
14 pF
240 max.
25
Ω
max.
0 to 70°C
±20 ppm
±50 ppm
External Components
The MK2771-16 requires a minimum number of external components for proper operation. Use a low inductance
ground plane, connect all GNDs to this. Connect 0.01µF decoupling caps on pins 5, 7, 8 and 22 directly to the
ground plane, as close to the MK2771-16 as possible. A series termination resistor of 33Ω may be used for each
clock output.The 13.500 MHz crystal must be connected as close to the chip as possible. The crystal should be a
parallel mode, pullable, with load capacitance of 14 pF. Consult IDT full specifications. Please obey Application
Note MAN05 for pullable crystal layout info except for the following: the MK2771-16 introduces a GND pin (pin #3)
between the pullable crystal pins. This ground should be brought in straight from the right side underneath the
device.
IDT™
VCXO AND SET-TOP CLOCK SOURCE
5
MK2771-16
REV F 122109
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