HY57V28820A
4Banks x 4M x 8bits Synchronous DRAM
DESCRIPTION
The Hyundai HY57V28820A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory appli-
cations which require large memory density and high bandwidth. HY57V28820A is organized as 4banks of
4,194,304x8.
HY57V28820A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
•
•
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM
Internal four banks operation
•
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full Page for Sequential Burst
•
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
•
•
ORDERING INFORMATION
Part No.
HY57V28820AT-6
HY57V28820AT-K
HY57V28820AT-H
HY57V28820AT-8
HY57V28820AT-P
HY57V28820AT-S
HY57V28820AT-10
HY57V28820ALT-6
HY57V28820ALT-K
HY57V28820ALT-H
HY57V28820ALT-8
HY57V28820ALT-P
HY57V28820ALT-S
HY57V28820ALT-10
Clock Frequency
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
100MHz
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
100MHz
Power
Organization
Interface
Package
Normal
4Banks x 4Mbits
x8
LVTTL
400mil 54pin TSOP II
Low power
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0/Dec.99
HY57V28820A
PIN CONFIGURATION
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
PIN DESCRIPTION
PIN
CLK
Clock
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
2
CKE
CS
BA0, BA1
Clock Enable
Chip Select
Bank Address
A0 ~ A11
Address
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
RAS, CAS, WE
DQM
DQ0 ~ DQ7
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 1.0/Dec.99
HY57V28820A
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 8 I/O Synchronous DRAM
Self refresh logic
& timer
Internal Row
counter
CLK
Row active
4Mx8 Bank3
Row
Pre
Decoders
4Mx8 Bank 2
X decoders
4Mx8 Bank 1
X decoders
4Mx8 Bank 0
X decoders
DQ0
DQ1
I/O Buffer & Logic
Sense AMP & I/O Gate
CKE
CS
RAS
CAS
WE
DQM
State Machine
Address buffers
X decoders
refresh
Column
Active
Memory
Cell
Array
Column
Pre
Decoders
DQ6
DQ7
Y decoders
Bank Select
Column Add
Counter
A0
A1
Address
Registers
Burst
Counter
A11
BA0
BA1
Mode Registers
CAS Latency
Data Out Control
Pipe Line Control
Rev. 1.0/Dec.99
3
HY57V28820A
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Short Circuit Output Current
Power Dissipation
Soldering Temperature
⋅
Time
T
A
T
STG
V
IN
, V
OUT
V
DD,
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260
⋅
10
Rating
°C
°C
V
V
mA
W
°C ⋅
Sec
Unit
Note :
Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION
(T
A
=0 to 70°C)
Parameter
Power Supply Voltage
Input High voltage
Input Low voltage
Symbol
V
DD
, V
DDQ
V
IH
V
IL
Min
3.0
2.0
-0.3
Typ
3.3
3.0
0
Max
3.6
V
DDQ
+ 0.3
0.8
Unit
V
V
V
Note
1
1,2
1,3
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
IH
(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.V
IL
(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION
(T
A
=0 to 70°C, V
DD
=3.3
±
0.3V, V
SS
=0V)
Parameter
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Symbol
V
IH
/ V
IL
Vtrip
tR / tF
Voutref
C
L
Value
2.4/0.4
1.4
1
1.4
50
Unit
V
V
ns
V
pF
1
Note
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 1.0/Dec.99
4
HY57V28820A
CAPACITANCE
(T
A
=25°C, f=1MHz)
-6/K/H
Parameter
Pin
Symbol
Min.
Input Capacitance
CLK
A0 ~ A11, BA0, BA1, CKE,
CS, RAS, CAS, WE, DQM
Data Input / Output Capacitance
DQ0 ~ DQ7
C
I1
CI
2
2.5
2.5
Max.
3.5
3.8
Min.
2.5
2.5
Max.
4
5
pF
pF
-8/P/S/10
Unit
C
I/O
4
6.5
4
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Ω
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I
(T
A
=0 to 70°C, V
DD
=3.3
±
0.3V)
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
I
LI
I
LO
V
OH
V
OL
Symbol
Min.
-1
-1
2.4
-
Max
1
1
-
0.4
Unit
uA
uA
V
V
Note
1
2
I
OH
= -4mA
I
OL
=+4mA
Note :
1.V
IN
= 0 to 3.6V, All other pins are not under test = 0V
2.D
OUT
is disabled, V
OUT
=0 to 3.6V
Rev. 1.0/Dec.99
5
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