RS8228/M28228
Octal ATM Transmission Convergence PHY Device
The RS8228 Octal ATM Transmission Convergence PHY device dramatically improves
performance for switch and access system low-speed ports by integrating all the ATM
physical layer processing functions found in the ATM Forum Cell Based Transmission
Convergence Sublayer specification (af-phy-0043.000) for eight individual ports. Each
port can be independently configured for operation at speeds ranging from 64 kbps to
52 Mbps. There is also a powerdown mode option for each TC port. A UTOPIA Level 2
Multi-PHY interface connects the device to the host switch or terminal system and
concentrates the ATM cell traffic onto one interface.
Typical system implementations center around the concentration of ATM cells over
standard PDH data rates such as T1/E1 lines, DS3/E3 lines, and multiple Digital
Subscriber Line (DSL) formats such as HDSL, ADSL or VDSL*. For each format,
external devices perform the appropriate Physical Media Dependent (PMD) layer
functions and present the RS8228 with a payload bit stream. The RS8228 then performs
all cell alignment functions on that bit stream. This gives system designers a simple,
modular, and low-cost architecture for supporting all UNI and NNI ATM interfaces below
52 Mbps. Because the RS8228 performs only the cell-based portion of the protocol
stack, designers can select the most integrated framer and Line Interface Unit (LIU)
available or reuse existing devices and software.
The RS8228 can also be used in combination with a Conexant Segmentation and
Reassembly (SAR) device. The RS8228 gluelessly connects to the SAR via the UTOPIA
and microprocessor interfaces. The device can be configured and controlled optionally
through a generic microprocessor interface. The RS8228’s chip-select feature allows the
microprocessor to select any of the framers through the PHY. The RS8228’s eight
interrupt inputs provide an internal mechanism for registering and controlling generated
interrupts.
* The term xDSL is used throughout this document to refer to the various DSL
formats as a group.
Distinguishing Features
•
•
8 cell-based TC Ports
UTOPIA interface
– Level 2
– 8/16 bit modes
– Multi-PHY
– Redundant channel
Glueless interface to Conexant’s:
– T1/E1 framers
– T3/E3 framers
– HDSL/SDSL devices
– SAR devices
Software reference material provided
8 chip selects for external framers
8 interrupt inputs for external
framers
Octet- and bit-level cell delineation
ITU I.432-compliant
Available in either 27 mm or 17 mm
BGA packages
•
•
•
•
•
•
•
Functional Block Diagram
Host
RS8228
LCs[7]
LCs[0]
LInt~[7]
LInt~[0]
Interrupt
Status
M
icroprocessor Interface
UTO
PIA
Level 2
M
ulti-PHY
Tx/Rx FIFO
4 Cells
A
TM
Layer
Device
8/16
UTOPIA
Level 2
Interface
External
PM
D
or
Fram
er
Framer
(Line)
Interface
External
PM
D
or
Fram
er
Cell Processor
Line
Interface
P 0
ort
G.804 Cell Fram
er
Cell Processor
Line
Interface
P 7
ort
G.804 Cell Fram
er
Tx/Rx FIFO
4 Cells
Data Sheet
Mindspeed Technologies
™
500234A
Ordering Information
Model Number
RS8228EBG
RS8228EBGB
M28228
Manufacturing
Part Number
28228-11
28228-12
28228-21
Product
Revision
A
B
A
Package
272-ball, 27 mm BGA
272-ball, 27 mm BGA
256-ball, 17 mm BGA
Operating Temperature
–40
°
C to 85
°
C
–40
°
C to 85
°
C
–40
°
C to 85
°
C
Revision History
Revision
A
Level
—
Date
November 2001
Description
This version has the 17 mm BGA information included.
Note that this document was previously released under
the document numbers 100064A and 100064B.
© 2001,
Mindspeed Technologies™, a Conexant business
All Rights Reserved.
Information in this document is provided in connection with Mindspeed Technologies (“Mindspeed”) products. These materials are
provided by Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no
responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at
any time, without notice. Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to its specifications and product descriptions.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as
provided in Mindspeed’s Terms and Conditions of Sale for such products, Mindspeed assumes no liability whatsoever.
THESE MATERIALS ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING
TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE
ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE
MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE
OF THESE MATERIALS.
Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or
selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any
damages resulting from such improper use or sale.
The following are trademarks of Conexant Systems, Inc.: Mindspeed Technologies™, the Mindspeed™ logo, and “Build It First”™.
Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties.
Third-party brands and names are the property of their respective owners.
For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at
www.mindspeed.com
which is incorporated by reference.
500234A
Mindspeed Technologies
™
Framer (Line) Interface Section
•
•
Programmable bit or byte synchronous serial interface
Direct connection to external Conexant components for:
– T1/E1
– DS3
– E3
– J2
– xDSL
– General purpose mode
– Interrupt and chip select signals for each external framer
Control and Status
Microprocessor Interface
•
•
•
•
•
•
•
•
Asynchronous SRAM-like interface mode
Synchronous, glueless Bt8233/RS8234 SAR interface mode
8-bit data bus
Open-drain interrupt output
Open-drain ready output
8–50 MHz operation
All control registers are read/write
Four programmable status indicator signals per port
Cell Alignment Framing Section
•
Supports ATM cell interface for:
– Circuit-based physical layer
– Cell-based physical layer
Passes or rejects idle cells or selected cells based on header
register configuration
Recovers cell alignment from Header Error Correction (HEC)
Performs single-bit HEC correction and single- or
multiple-bit detection
Generates cell status bits, cell counts, and error counts
Inserts headers and generates HEC
Inserts idle cells when no traffic is ready
Counters/Status Register Section
•
•
•
•
Summary interrupt indications
Configuration of interrupt enables
One-second counter latching
Counters for:
– LOCD events
– Corrected HEC errors
– Uncorrected HEC errors
– Transmitted cells
– Matching received cells
– Non-matching received cells
•
•
•
•
•
•
UTOPIA Level 2 Interface
•
•
•
•
PHY cell to UTOPIA interface
50 MHz maximum clock rate
8/16-bit data path interface
Multi-PHY capability
500234A
Mindspeed Technologies
™
500234A
Mindspeed Technologies
™
Table of Contents
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1.0
Product Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
1.3
1.4
1.5
Application Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Logic Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
27 mm Pin Diagram and Definitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
17 mm Pin Diagram and Definitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Block Diagram and Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
2.0
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
ATM Cell Processor
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1
2.1.2
ATM Cell Transmitter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1.1
HEC Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
ATM Cell Receiver
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.2.1
Cell Delineation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.2.2
Cell Screening
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Cell Scrambler
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.3.1
SSS Scrambling
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.3.2
DSS Scrambling
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
T1/E1 Timing for the CX28229
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
DS3 Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
E3/G.832 34.368 Mbps Interface.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
J2 6.312 Mbps Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
General Purpose Mode Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
UTOPIA Transmit and Receive FIFOs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
UTOPIA 8-bit and 16-bit Bus Widths
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
UTOPIA Parity
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
UTOPIA Multi-PHY Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
UTOPIA Addressing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Handshaking
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.1.3
2.2
Framing Modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.3
UTOPIA Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
500234A
Mindspeed Technologies
™
v
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