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RS8250/1/2/3/4/5
ATM Physical Interface
Devices - ATM PHY
datasheet
PROVIDING
HIGH
SPEED
MULTIMEDIA
CONNECTIONS
September 1998
Preliminary Information
This document contains information on a product under development. The parametric information contains target
parameters that are subject to change.
RS8250/1/2/3/4/5
ATM Physical Interface Devices—ATM PHY
The RS825x is a family of six 155 Mbps (OC-3/STM-1) ATM-SONET Physical Layer
(PHY) devices with an integrated, low-jitter PLL clock and data recovery circuit.
These devices have optimized SONET framer functions for mapping ATM cells to
SONET payloads for edge switch applications, and optional enhanced feature sets
for ATM-WAN access applications. They provide ATM Forum compliant service
termination, and map the 53-byte cells from an ATM switch fabric or an adaptation
layer processor (SAR) into the SONET payload. Available in single, dual, and quad
port packages, as well as LAN and WAN versions, the RS825x devices are tailored
to meet a wide variety of ATM OC-3 applications, including WAN terminals, ATM
LAN and WAN switches, ATM OC-3 NICs, and Ethernet-ATM uplink cards.
The RS825x family thus consists of six devices, with three devices in each of
two categories, WAN and LAN. All references to the RS825x in this document
apply to the entire family of RS825x devices, unless otherwise noted.
The RS825x uses an ATM Forum UTOPIA Level 2 compliant host interface
designed for a multi-PHY environment. The ATM framer provides G.804 cell
processing, with HEC generation, checking and alignment operations. Each port
provides a 155 Mbps SONET termination with all of the counters needed for
capturing both SONET and ATM error events as specified by the ATM Forum. A
proprietary protection scheme allows for near-instantaneous switching between
active and stand-by PHYs.
The RS825x family uses a Pseudo-Emitter Coupled Logic (PECL) line interface,
that is compliant with the ATM Forum’s WIRE definition. Thus, designers can
connect directly to either fiber optic or Cat 5 Physical Media Dependent (PMD)
devices. For diagnostics, three loopback modes are provided: source loopback,
line loopback before the ATM processor, and line loopback at the UTOPIA block. In
addition, the RS825x can generate BIP-8 errors and insert invalid HECs.
The WAN versions of the device (RS8250/2/4), support full compliance with the
jitter requirements of Bellcore’s GR-253-CORE, as well as support for Automatic
Protection Switching (APS) using the K1/K2 overhead octets and a Bit Error Rate
(BER) integrator. The WAN devices also support access to the S1 octet for system
timing, as well as data transmission/reception over the Data Link message
channels, D1-D3 and D4-D12.
Distinguishing Features
•
•
•
•
•
•
•
Synthesizes a 155.52 MHz clock
from an 8 kHz input.
UTOPIA Level 2 interface.
Meets ITU, ANSI, and ATM Forum
standards.
ATM Forum WIRE interface for PMDs
using PECL.
D1-D3, D4-D12 external data link
(WAN only).
Supports APS (K1/K2 bytes)(WAN
only).
SRAM-style microprocessor
interface for all control and
configuration registers.
Glueless interface to the Bt/RS823x
segmentation and reassembly
devices.
JTAG (IEEE 1149.1a-1993) compliant
8 kHz and 19.44 MHz selectable sync
inputs and outputs.
SONET overhead processing.
Automatic collection of one-second
statistics.
Low power consumption-500 mW/
port.
Rapid start after reset.
Reference software provided.
3.3 V, (-40
°
to 85
°
C).
Packages: 128-pin TQFP (RS8251),
156-pin BGA (RS8250), and 256-pin
BGA (RS8252/3/4/5).
•
•
•
•
•
•
•
•
•
•
Applications
•
•
•
Switches, Hubs, Routers
LAN NIC cards
DSLAM uplinks
RS8250/1 Functional Block Diagram
Microprocessor Bus
Line Interface
Microprocessor Interface
PMD
Interface
8 Bits
RS8250/1
Host Interface
Tx
4-cell
FIFO
8/16 Bits
ATM WIRE
Interface
SONET Framer and
Overhead Processor
STS-3c/STM-1
(GR-253-CORE)
ATM Formatter
(G.804 Cell Processing)
UTOPIA
Level 2
UTOPIA
Level 2
Interface
8/16 Bits
Clock
Recovery
Rx
4-cell
FIFO
Preliminary N825xDSA
Ordering Information
Manufacturing
Part Number
28250-14
28251-13
R7171-11
R7172-11
R7173-11
R7174-11
R7173-12
Product
Revision
C
B
A
A
A
A
B
Model Number
RS8250EBGC
RS8251ETFB
RS8252EBG
RS8253EBG
RS8254EBG
RS8255EBG
RS8254EBGB
Package
156-pin, 15 mm BGA
128-pin TPQFP
256-pin, 35 mm BGA
256-pin, 35 mm BGA
256-pin, 35 mm BGA
256-pin, 35 mm BGA
256-pin, 35 mm BGA
Operating Temperature
-40
°
C to 85
°
C
-40
°
C to 85
°
C
-40
°
C to 85
°
C
-40
°
C to 85
°
C
-40
°
C to 85
°
C
-40
°
C to 85
°
C
-40
°
C to 85
°
C
Copyright © 1998 Rockwell Semiconductor Systems, Inc. All rights reserved.
Print date: September 1998
Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve
performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no
responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by its implication or otherwise under any patent or intellectual property rights of Rockwell
Semiconductor Systems, Inc.
Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or
systems where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal
injury or death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc.
products for use in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc.
for any damages resulting from such improper use or sale.
Bt is a registered trademark of Rockwell Semiconductor Systems, Inc.
Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
Preliminary N825xDSA
RS825x Features
Line Interface
• ATM Forum WIRE interface specification
compliant
• PECL I/O, compatible with PMD optical and
UTP interface devices
• Clock recovery from NRZ input data
• Recovery of receive-octet alignment and
octet clock from F6/28 framing pattern
• Select transmit clock from input or
recovered receive clock
• PMD (line) and Framer (source) loopbacks
for diagnostic testing
• Loss of Signal (LOS) detection
• 8 kHz or 19.44 MHz reference clock
UTOPIA Level 2 Interface
•
•
•
•
•
•
PHY cell to UTOPIA interface
50 MHz maximum data rate
8/16-bit data path interface
Multi-PHY support
Mode-compatible with UTOPIA level 1
Configurable cell buffer depth
SONET STS_3c/STM-1 Framer
Section Overhead Octets Supported
Transmit
A1/A2
J0
Z0, Z0
B1
D1, D2, D3
F6/28 hex or disable 00
01 hex or 64-byte trace buffer
02, 03 hex
Calculated, error insertion
00 hex or external data link (WAN only)
Receive
Monitor out of frame state machine
Monitor Rx trace buffer, interrupt on change
Not checked
Checked, errors counted
External data link (WAN only)
Line Overhead Octets Supported
Transmit
Receive
Full GR.253 pointer processor
Used in pointer processor
Checked, errors counted
Checked, interrupt on change (WAN only)
External data link (WAN only)
Checked, interrupt on change (WAN only)
Checked, errors counted
H1/H2
H3
B2
K1/K2
D4-D12
S1
M1
620A/93FF hex pointer
Set to 00
Calculated, error insertion
Insertable via register (WAN only)
00 hex or external data link (WAN only)
Insertable via register (WAN only)
Line FEBE inserted
Path Overhead Octets Supported
Transmit
J1
B3
C2
G1
00 hex or 64-byte trace buffer
Calculated, error insertion
13 hex for ATM mapping
Path FEBE, RDI inserted
Receive
Monitor Rx trace buffer, interrupt on change
Checked, errors counted
Checked for 01 or 13 hex
Checked, errors counted, status
Preliminary N825xDSA
Sonet Framer Functions
• Recovers frame location using F6/28
framing pattern.
• Processes pointer to locate payload
envelope.
• Provides OOF, LOP, and AIS status.
• Provides frame and payload position
information to other blocks.
• Generates clocks and frame
counters.
• Maps cell data into payload envelope.
• Generates all section, line, and path
overhead and alarms.
• Performs cell and frame scrambling
before transmission.
• Detects and integrates alarms for
reporting in status registers.
• Detects BIP and FEBE errors for error
counters.
• Recovers D1-D3 and D4-D12 data
link (WAN only).
Cell Alignment Framing Section
• Recovers cell alignment from HEC.
• Performs HEC error correction.
• Matches idle/desired cell headers and
generates write strobes and cell sync
for UTOPIA interface.
• Generates cell status bits, cell counts,
and error counts.
• Reads cell data from the UTOPIA FIFO.
• Inserts headers and generates HEC.
• Inserts idle cells when no traffic is
ready.
Support for Automatic Protection Switch-
ing (APS) (WAN only)
• Register control allows for support of
APS.
• K1/K2 Transmit control register allows
transmission of any value.
• Separate control bits for AIS, line FERF.
• K1/K2 receive status register allows
observation of incoming octet values.
• Maskable interrupt on any change in
received value.
• Software interrupt routine can easily
implement APS protocol.
• Signal Fail/Signal Detect BER threshold
monitoring.
Control and Status
Microprocessor Interface
• SRAM-like interface mode with high
performance or
low-power access selection
• Glueless RS8233/4 SAR interface
mode
• 8-bit data bus
• Open-drain interrupt output
Counters/Status and Interrupt Registers
•
•
•
•
•
Summary interrupt indications
Configuration of interrupt enables
One-second status latching
One-second counter latching
Eight general purpose outputs,
configurable as status indicator pins
The following diagram is a Network Interface Card (NIC) application of the RS825x.
Bt/RS823x
PCI
Bus
UTOPIA Bus
Interface
PCI
Interface
Local Bus
Interface
UTOPIA Bus
RS825x
UTOPIA Interface
PMD Interface
Local Bus
Microprocessor
Interface
PMD
Device
Fiber
or
Cat 5
SRAM
Preliminary N825xDSA
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