iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72PBG
32Mx72 DDR2 SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR2 Data rate = 667, 533, 400
Available in Industrial, Enhanced and Military Temp
Package:
•
255 Plastic Ball Grid Array (PBGA), 25 x 32mm
•
1.27mm pitch
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
1.8V
±0.1V
power supply and I/O (VCC/VCCQ)
Programmable CAS latency: 3, 4, 5, or 6
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
Organized as 32M x 72 w/ support for x80
Weight: AS4DDR232M72PBG ~ 3.5 grams typical
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only
THIS PRODUCT IS SUBJECT TO MICROSS PCN 1027.
RECOMMEND AS4DDR232M72APBG AS REPLACEMENT.
BENEFITS
SPACE conscious PBGA defined for easy
SMT manufacturability (50 mil ball pitch)
Reduced part count
47% I/O reduction vs Individual CSP approach
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradable to 64M x 72 density
(consult factory for info on
AS4DDR264M72PBG)
Configuration Addressing
Parameter
Configuration
Refresh Count
Row Address
Bank Address
Column Address
32 Meg x 72
8 Meg x 16 x 4 Banks
8K
8K (A0 A12)
4 (BA0 BA1)
1K (A0 A9)
FUNCTIONAL BLOCK DIAGRAM
Ax, BA0-1
ODT
VRef
VCC
VCCQ
VSS
VSSQ
VCCL
VSSDL
CS0\
CS1\
CS2\
CS3\
CS4\
UDMx, LDMx
UDSQx,UDSQx\
LDSQx, LDSQx\
RASx\,CASx\,WEx\
CKx,CKx\,CKEx
A
2
2
2
3
3
A
VCCL
VSSDL
2
2
2
3
3
B
VCCL
VSSDL
2
2
2
3
3
C
VCCL
VSSDL
2
2
2
3
3
2
2
2
3
3
D
VCCL
VSSDL
DQ64-79
DQ0-15 B
DQ16-31 C
DQ32-47 D
DQ48-63
AS4DDR232M72PBG
Rev. 2.4 08/10
1
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72PBG
SDRAM-DDRII PINOUT TOP VIEW
Rev. A, 07/06 - X72/X80
Rev. B, 10/06 - X72/X80
1
a
b
c
d
e
f
g
h
j
k
l
m
n
p
r
t
DQ1
DQ3
DQ6
DQ7
CAS0\
CS0\
VSS
VSS
CLK3\
NC
DQ56
DQ57
DQ60
DQ62
VSS
1
2
DQ0
DQ2
DQ4
DQ5
LDM0
WE0\
RAS0\
VSS
VSS
CKE3
CLK3
UDM3
DQ58
DQ59
DQ61
DQ63
2
3
DQ14
DQ12
DQ10
DQ8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DQ55
DQ53
DQ51
DQ49
3
4
DQ15
DQ13
DQ11
DQ9
UDM0
CLK0
CKE0
VCCQ
VCCQ
CS3\
CAS3\
WE3\
DQ54
DQ52
DQ50
DQ48
4
5
VSS
VSS
VCC
VCCQ
6
VSS
VSS
VCC
VCCQ
7
A9
A0
A2
A12/NC
8
A10
A7
A5
DNU
BA0
9
A11
A6
A4
DNU
BA1
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
CAS4\
DQ71
DQ69
DQ67
DQ65
9
10
A8
A1
A3
DNU
11
VCCQ
VCC
VSS
VSS
12
VCCQ
VCC
VSS
VSS
VREF
RAS1\
CAS1\
VCC
VCC
CLK2\
13
DQ16
DQ18
DQ20
DQ22
LDM1
WE1\
CS1\
VSS
VSS
CKE2
CLK2
UDM2
DQ41
DQ43
DQ45
DQ47
13
14
DQ17
DQ19
DQ21
DQ23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQ40
DQ42
DQ44
DQ46
14
15
DQ31
DQ29
DQ27
DQ26
NC
UDM1
CLK1\
VCCQ
VCCQ
RAS2\
WE2\
LDM2
DQ37
DQ36
DQ34
DQ32
15
16
VSS
DQ30
DQ28
DQ25
DQ24
CLK1
CKE1
VCC
VCC
CS2\
a
b
c
d
e
f
g
h
j
k
UDQS3 LDQS0 UDQS0
LDQS1 UDQS1
UDQS1\ LDQS1\
VSSQ
VSSQ
VSSQ
VSSQ
NC
NC
NC
NC
LDQS3 UDQS3\ LDQS0\ UDQS0\
CLK0\
VSS
VSS
LDQS3\
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
LDQS4\
UDM4
DQ73
DQ75
DQ77
DQ79
7
VSSQ
VSSQ
VSSQ
VSSQ
NC
CLK4
DQ72
DQ74
DQ76
DQ78
8
LDQS4 UDQS4\
RAS3\
LDM3
UDQS4
VSS
VCC
VCCQ
5
ODT
CKE4
CLK4\
VSS
VCC
VCCQ
6
LDQS2\ UDQS2\ LDQS2
WE4\
DQ70
DQ68
DQ66
DQ64
10
RAS4\
LDM4
VCC
VSS
VSS
11
CS4\
UDQS2
VCC
VSS
VSS
12
CAS2\
l
DQ39
DQ38
DQ35
DQ33
VCC
m
n
p
r
t
Ground
Array Power
D/Q Power
Address
Data IO
Level REF.
CNTRL
ADDRESS-DNU
UNPOPULATED
NC
AS4DDR232M72PBG
Rev. 2.4 08/10
2
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72PBG
BGA Locations
L6
F4, F16, G5, G15, K12
L13, L2, K1, M8, N6
G4, G16, K13, M6, K2
G1, G13, K16, K4, M12
F12, G2, K15, L5, M11
F1, G12, M9, L16, L4,
F2, F13, L15, M4, M10
E4, F15, M13, M7, M2
E2, E13, M15, M5, N11
E5, E7, E11, N12, N5
F6, F8, F10, K6, L11
E6, E10, F5, K5, L12
F7, F11, G6, L7, L10
CKEx
CSx\
RASx\
CASx\
Wex\
UDMx
LDMx
UDQSx
UDQSx\
LDQSx
LDQSx\
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
Clock enable which activates all on silicon clocking circuitry
Chip Selects, one for each 16 bits of the data bus width
Command input which along with CAS\, WE\ and CS\ define operations
Command input which along with RAS\, WE\ and CS\ define operations
Command input which along with RAS\, CAS\ and CS\ define operations
One Data Mask cntl. for each upper 8 bits of a x16 word
One Data Mask cntl. For each lower 8 bits of a x16 word
Data Strobe input for upper byte of each x16 word
Differential input of UDQSx, only used when Differential DQS mode is enabled
Data Strobe input for lower byte of each x16 word
Differential input of LDQSx, only used when Differential DQS mode is enabled
Array Address inputs providing ROW addresses for Active commands, and
the column address and auto precharge bit (A10) for READ/WRITE commands
Symbol
ODT
CKx, CKx\
Type
CNTL Input
CNTL Input
Description
On-Die-Termination: Registered High enables on data bus termination
Differential input clocks, one set for each x16bits
A7, A8, A9, A10, B7,
Ax
Input
B8, B9, B10, C7, C8,
C9, C10, D7
D8, D9, D10
DNU
Future Input
E8, E9
BA0, BA1
Input
A2, A3, A4, A13, A14,
DQx
Input/Output
A15, B1, B2, B3, B4,
B13, B14, B15, B16,
C1, C2, C3, C4, C13,
C14, C15, C16, D1, D2,
D3, D4, D13, D14, D15,
D16, E1, E16, M1, M16,
N1, N2, N3, N4, N7, N8,
N9, N10, N13, N14,
N15, N16, PP1, P2, P3,
P4, P7, P8, P9, P10,
P13, P14, P15, P16,
R1, R2, R3, R4, R7, R8,
R9, R10, R13, R14,
R15, R16, T2, T3, T4,
T7, T8, T9, T10, T13,
T14, T15
E12
Vref
Supply
B11, B12, C5, C6,E3,
VCC
Supply
F3, G3, H3, H12, H16,
J3, J12, J16, K3, L3,
M3, P11, P12, R5, R6,
T16
A11, A12, D5, D6, H4,
VCCQ
Supply
H15, J4, J15, T5, T6
A5, A6, A16, B5, B6,
VSS
Supply
C11, C12, D11, D12,
E14, F14, G14, H1, H2,
H14, J1, J2, J5, J13,
J14, K14, L14, M14, P5,
P6, R11, R12, T1, T11,
T12, H5, H13
G7, G8, G9, G10, H7,
VSSQ
Supply
H8, H9, H10, J7, J8, J9,
J10, K7, K8, K9, K10
E15, F9, G11, H6, H11,
NC
J6, J11, K11, L1, L8, L9,
A1
UNPOPULATED
AS4DDR232M72PBG
Rev. 2.4 08/10
Bank Address inputs
Data bidirectional input/Output pins
SSTL_18 Voltage Reference
Core Power Supply
I/O Power
Core Ground return
I/O Ground return
No connection
Unpopulated ball matrix location (location registration aid)
3
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72PBG
DESCRIPTION
The 2.4Gb DDR2 SDRAM, a high-speed CMOS, dynamic
random-access memory containing 2,684,354,560 bits.
Each of the five chips in the MCP are internally configured
as 4-bank DRAM. The block diagram of the device is
shown in Figure 2. Ball assignments and are shown in
Figure 3.
The 2.4Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer
two data words per clock cycle at the I/O balls. A
single read or write access for the x72 DDR2 SDRAM
effectively consists of a single 4n-bit-wide, one-clock-
cycle data transfer at the internal DRAM core and four
corresponding
n-bit-wide,
one-half-clock-cycle data
transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted
externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR2
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. There
are strobes, one for the lower byte (LDQS, LDQS#) and
one for the upper byte (UDQS, UDQS#).
The MCP DDR2 SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data
is referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR2 SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed.
The address bits registered coincident with the READ
or WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR2 SDRAM provides for programmable read
or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight with
another read, or a burst write of eight with another
write.
An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent
operation, thereby providing high, effective bandwidth by
hiding row precharge and activation time.
A self refresh mode is provided, along with a power-
saving power-down mode.
All inputs are compatible with the JEDEC standard for
SSTL_18. All full drive-strength outputs are SSTL_18-
compatible.
•
The functionality and the timing specifications
discussed in this data sheet are for the DLLenabled
mode of operation.
•
Throughout the data sheet, the various figures and
text refer to DQs as ¡°DQ.¡± The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise. Additionally, each chip
is divided into 2 bytes, the lower byte and upper
byte. For the lower byte (DQ0¨CDQ7), DM refers to
LDM and DQS refers to LDQS. For the upper byte
(DQ8¨CDQ15), DM refers to UDM and DQS refers to
UDQS.
•
Complete functionality is described throughout
the document and any page or diagram may have
been simplified to convey a topic and may not be
inclusive of all requirements.
•
Any specific requirement takes precedence over a
general statement.
GENERAL NOTES
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized
in a predefined manner. Operational procedures other
than those specified may result in undefined operation.
The following sequence is required for power up and
initialization and is shown in Figure 4 on page 8.
1. Applying power; if CKE is maintained below 0.2 x
V
CCQ
, outputs remain disabled. To guarantee R
TT
(ODT resistance) is off, V
REF
must be valid and a
low level must be applied to the ODT ball (all other
inputs may be undefined, I/Os and outputs must be
less than V
CCQ
during voltage ramp time to avoid
DDR2 SDRAM device latch-up). At least one of the
AS4DDR232M72PBG
Rev. 2.4 08/10
4
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72PBG
following two sets of conditions (A or B) must be met to
obtain a stable supply state (stable supply defi ned as
V
C C
, V
C C Q
, V
R E F
, a n d V
T T
a r e b e t w e e n t h e i r
minimum and maximum values as stated in Table20);
A. (single power source) The V
CC
voltage ramp from
300mV to V
CC
(MIN) must take no longer than
200ms; during the V
CC
voltage ramp, |VCC - VCCQ|
±
0.3V. Once supply voltage ramping is complete
(when V
CCQ
crosses V
CC
(MIN)), Table 20
specifications apply.
• V
CC
, V
CCQ
are driven from a single power
converter output
• V
TT
is limited to 0.95V MAX
• V
REF
t r a c k s V
CCQ/2
; V
REF
m u s t b e w i t h i n
±
0.3V with respect to V
CCQ/2
during supply ramp
time
• V
CCQ
> V
REF
at all times
B. (multiple power sources) V
CC
> V
CCQ
must be
maintained during supply voltage ramping, for both
AC and DC levels, until supply voltage ramping
completes (V
CCQ
crosses V
CC
[MIN]). Once supply
voltage ramping is complete, Table 20 specifications
apply.
• Apply V
CC
before or at the same time as
V
CCQ
; V
CC
voltage ramp time must be < 200ms
from when V
CC
ramps from 300mV to V
CC
(MIN)
• Apply V
CCQ
before or at the same time as V
TT
; the
V
CCQ
voltage ramp time from when V
CC
(MIN) is
achieved to when V
CCQ
(MIN) is achieved must be
<500ms; while V
CC
is ramping, current can be
supplied from V
CC
through the device to V
CCQ
• VREF must track VCCQ/2, VREF must be within
±
0.3V with respect to V
CCQ/2
during supply ramp
time; V
CCQ
> V
REF
must be met at all times
• Apply V
TT
; The V
TT
voltage ramp time from when
V
CCQ
(MIN) is achieved to when V
TT
(MIN) is achieved
must be no greater than 500ms
2. For a minimum of 200
μ
s after stable power nd clock
(CK, CK#), apply NOP or DESELECT commands and
take CKE HIGH.
3. Wa i t a m i n i m u m o f 4 0 0 n s , t h e n i s s u e a
PRECHARGE ALL command.
4. Issue an LOAD MODE command to the EMR(2). (To
issue an EMR(2) command, provide LOW to BA0,
provide HIGH to BA1.)
5. Issue a LOAD MODE command to the EMR(3). (To
issue an EMR(3) command, provide HIGH to BA0 and
BA1.)
6. Issue an LOAD MODE command to the EMR to enable
DLL. To issue a DLL ENABLE command, provide LOW
to BA1 and A0, provide HIGH to BA0. Bits E7, E8, and
E9 can be set to “0” or “1”; Micron recommends setting
them to “0”.
7. Issue a LOAD MODE command for DLL RESET. 200
cycles of clock input is required to lock the DLL. (To
issue a DLL RESET, provide HIGH to A8 and provide
LOW to BA1, and BA0.) CKE must be HIGH the entire
time.
8. Issue PRECHARGE ALL command.
9. Issue two or more REFRESH commands, followed
by a dummy WRITE.
AS4DDR232M72PBG
Rev. 2.4 08/10
5
Micross Components reserves the right to change products or specifications without notice.
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