LHF00L02
Data Sheet
FEATURES
• Conforms to Intel LPC Interface Specification 1.0
• Optimized Array Block Architecture
– Fifteen 64KB Uniform Blocks
– Eight 8KB Boot Sectors
– Boot Sector Data protection for each 8KB Sector
– Full Chip Erase (A/A Mode Only)
• V
CC
= 3.0 V - 3.6 V Operation
• Extended Cycling Capability
– Minimum 100,000 Block Erase Cycles
• Low Power Consumption (LPC Interface)
– Standby Current: 15 µA (MAX.)
– Read Current: 15 mA (MAX.)
– Erase or Program Current: 25 mA (MAX.)
• Erase or Program Operation
– Byte Program Time: 25 µs (TYP.)
– Sector Erase Time: 0.6 sec. (TYP.)
– Block Erase Time: 1.2 sec. (TYP.)
– Full Chip Erase Time: 40 sec. (TYP.)
– Sector Rewrite Time: 0.8 sec. (TYP.)
– Block Rewrite Time: 2.8 sec. (TYP.)
• Operating Temperature 0°C to +85°C
• CMOS Process (P-type silicon substrate)
• Two Operational Modes
– Low Pin Count (LPC) Interface mode for In-system
Operation
– Address/Address Multiplexed Interface (A/A)
Mode for Production Erasing and Programming
• LPC Interface Mode
– Five-Signal Communication Interface Supporting
Byte Read and Write
– 33 MHz Clock Frequency Operation
– WP and TBL Pins Provide Hardware Data
protection for Entire Chip and/or Boot Sector
– Status Polling and Toggle Bit for End-of-Write
Detection
– Five GPI Pins for System Design Flexibility
– ID Pins for Mutli-chip Selection
8M LPC Flash Memory
• Multi Byte Read Mode (LPC)
– Maximum 128-Byte Sequential Read Operation
for Data Transfer
• A/A Interface Mode
– 11 Pin Multiplexed Address and 8-pin Data I/O
Interface
– Supports Fast In-system or PROM Programming
for Manufacturing
• CMOS and PCI I/O Compatibility
• ETOX™ Nonvolatile Flash Technology
• Not Designed or Rated as Radiation Hardened
DESCRIPTION
The LHF00L02 is offered in a 32-pin TSOP (normal
bend) package. Refer to Figure 1 for pinouts and Table
1 for pin descriptions.
32-PIN TSOP
TOP VIEW
(NC)
(NC)
(NC)
(CE)
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
WE
V
CC
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
(INIT)
(LFRAME)
(V
CC
)
(RES)
(RES)
(RES)
(RES)
(LAD
3
)
(LAD
2
)
(LAD
1
)
(LAD
0
)
(ID
0
)
(ID
1
)
(ID
2
)
(ID
3
)
(MODE) MODE
(GPI
4
)
(LCLK)
(V
CC
)
(RST)
(GPI
3
)
(GPI
2
)
(GPI
1
)
(GPI
0
)
(WP)
(TBL)
A
10
R/C
V
CC
RST
A
9
A
8
A
7
A
6
A
5
A
4
(RY/BY) RY/BY
GND (GND)
NOTE:
Functions inside ( ) are for LPC mode.
LHF00L02-1
Figure 1. LHF00L02 Pinout
* ETOX is a trademark of Intel Corporation.
Data Sheet
1
LHF00L02
8M LPC Flash Memory
Table 1. Pin Descriptions
SYMBOL
TYPE
INTERFACE
A/A
•
LPC
•
DESCRIPTION
Reset
When LOW (V
IL
), RST resets internal automation and inhibits erase and program
operations, which provides data protection. RST HIGH (V
IH
) enables normal operation.
After power-up or reset mode, the device is automatically set to read array mode.
Mode
This pin determines which interface is operational. This pin must be held HIGH
(V
IH
) for A/A mode and LOW (V
IL
) for LPC mode. This pin is internally pulled-down with
a resistor between 20 kΩ - 100 kΩ.
Initialize
This is a second reset pin for in-system use. This pin is internally combined
with the RST pin; if this pin or RST is driven LOW, identical operations occur.
Chip Enable
This signal must be asserted to select the device. When CE is LOW, the
device is enabled. When CE is HIGH, the device is placed in low power (standby) mode.
Frame
Indiciates the start of a data transfer operation. This pin is also used to abort
an LPC cycle in process.
Address and Data
Provides address and data for LPC mode.
RST
Input
MODE
Input
•
•
INIT
CE
LFRAME
LAD
3
- LAD
0
LCLK
ID
3
- ID
0
GPI
4
- GPI
0
TBL
Input
Input
Input
Input/
Output
Input
Input
•
•
•
•
•
•
Clock
To provide a clock input to the control unit.
Identification Inputs
These four pins are part of the mechanism that allows multiple
parts to be attached to the same bus. The strapping of these pins is used to identify the
component. These pins are internally pulled-down with a resistor between 20 kΩ - 100 kΩ.
General Purpose Inputs
These individual inputs can be used for additional flexibility.
The state of these pins can be read through GPI registers.
Top Boot Lock
When LOW, prevents erasing and programming to the boot sectors
at top (highest address) of memory. When TBL is HIGH, it disables hardware data pro-
tection for the the boot sectors. Do not float this pin.
Write Protect
When LOW, prevents erasing and programming to all blocks other than
top boot sector. When WP is HIGH, it disables hardware data protection for these
blocks. Do not float this pin.
Reserved
Allows pins to float.
Output Enable
Gates the device’s outputs during a read cycle.
Write Enable
Controls writes to the memory array. Data is latched on the rising edge
of WE.
Row/Column Select
For A/A interface mode, this pin determines whether the ad-
dress pins are porting to the row address, or to the column address.
Address Inputs
Inputs for low-order addresses during read and write operations. Ad-
dresses are internally latched by R/C during an erase or program cycle. These address-
es share the same pins as the high-order address inputs.
Data Inputs/Outputs
Inputs data and commands during write cycles, outputs data
during memory array, status register and identifier code reads. Data pins float to high-
impedance (High-Z) when the chip or outputs are deselected. Data is internally latched
during an erase or program cycle.
Input
•
Input
•
WP
RES
OE
WE
R/C
Input
•
•
Input
Input
Input
•
•
•
A
10
- A
0
Input
•
DQ
7
- DQ
0
Input/
Output
Open
Drain
Output
Supply
Supply
•
RY/BY
•
•
Ready/Busy
This output pin is a reflection LPF bit 7 in the status register. This pin is
used to determine the erase or program completion. This pin must be pulled-up with an
external resistor on board.
Device Power Supply
(3.0 V - 3.6 V): With V
CC
≤
V
LKO,
all write attempts to the flash
memory are inhibited. Device operations at invalid V
CC
voltage (refer to DC Character-
istics) produce spurious results and should not be atempted.
Ground
Do not float any ground pins.
No Connect
Lead is not internally connected; it may be driven or foated.
V
CC
GND
NC
•
•
•
•
•
•
2
Data Sheet
8M LPC Flash Memory
LHF00L02
DEVICE OPERATION
Mode Selection
The LHF00L02 can operate in two interface modes:
• LPC interface mode for in-system erasing and pro-
gramming
• Address/Address Multiplexed (A/A) interface mode
for factory erasing and programming.
The state of the MODE pin determines which inter-
face is in use. If the MODE pin is set HIGH, the device is
in A/A mode; if the MODE pin is set LOW, the device is
in the LPC mode. The MODE selection pin must be con-
figured prior to device operation.
LPC Mode
The LPC mode uses a 5-signal communication inter-
face, 4-bit address/data bus, LAD
3
- LAD
0
, and a control
line, LFRAME, to control operation. Cycle type opera-
tions such as Memory Read and Memory Write are
defined in Intel Low Pin Count Interface Specification,
Rev. 1.0. Erase and Program command sequences are
incorporated into the standard LPC memory cycle.
LPC signals are transmitted via the 4-bit Address/
Data bus (LAD
3
- LAD
0
), and follow a particular
sequence, depending on whether they are Read or
Write operations. The standard LPC memory cycle is
defined in Table 2 and Table 3.
CE, LFRAME
The CE (Chip Enable) pin, controls read and write
access. To enable the output, the CE pin must be
driven LOW one cycle prior to LFRAME being drive
LOW. For write (erase or program) cycles, the CE pin
must remain LOW during the internal operation. When
CE is HIGH, the chip is placed in standby mode.
The LFRAME signifies the start of a frame or the ter-
mination of a broken frame. Asserting LFRAME for one
or more clock cycle and driving a valid ‘START’ value
on LAD
3
- LAD
0
will initiate operation. The device
enters standby mode when LFRAME and CE are HIGH
and no internal operation is in progress.
ABORT MECHANISM
If LFRAME is driven LOW for 4 clock cycles during a
LPC cycle, the cycle will be terminated and the device
will wait for the ABORT command. To return the device
to the ready mode, the host must drive LAD
3
- LAD
0
with ‘1111b’ (‘ABORT’ command) while LFRAME is
driven LOW, and LAD
3
- LAD
0
must remain unchanged
until LFRAME goes to V
IH
(refer to Figure 18). When an
abort procedure is performed between two command
write cycles, such as sector/block erase or byte pro-
gram, the device turns the bus around to the host but
the command termination for the internal operation is
not guaranteed. If the system needs to abort after the
first command cycle, the host must write ‘FFH’ and
check the status register after performing the abort pro-
cedure. The status register indicates termination of
internal operation and error conditions. If an abort
occurs during the internal write cycle, the data may be
incorrectly programmed or erased. The write operation
must complete prior to initiation of an abort command.
Check the write status with status polling (DQ
7
) or tog-
gle bit (DQ
6
). One other option is to wait for the fixed
write time to expire.
Status Polling DQ
7
(LPC Mode, A/A Mode)
When the device is performing an internal operation
(program, erase, etc.), WSM (Write State Machine)
status bit DQ
7
(SR.7) will read ‘0’. Once the internal
operation is completed, DQ
7
will read ‘1’. The SR.7 bit
can be polled to find the end of the operation. The other
status bits (SR.5-0) should not be checked until the
WSM completes the operation and the status bit SR.7
is ‘1’. Refer to Table 13 for status register definitions.
Toggle Bit DQ
6
(LPC Mode, A/A Mode)
During any automatic internal operation (program,
erase, etc.) consecutive attempts to read DQ
6
(SR.6)
will produce alternating ‘0’s and ‘1’s; i.e., toggling
between ‘0’ and ‘1’. When the internal operation is com-
pleted, the value will be static.
Data Sheet
3
LHF00L02
8M LPC Flash Memory
LPC MEMORY CYCLE FIELD DEFINITIONS
Table 2. LPC Read Cycle Field Definitions
FIELD
START
CYCTYPE
CLOCKS
1
1
LAD
3
- LAD
0
DIRECTION
Input
Input
DESCRIPTION
Start of Cycle: ‘0000b’ appears on LPC bus to indicate the start.
Cycle Type: LAD
3
- LAD
2
must be ‘01b’ for memory cycle. LAD
1
indicates the direction
of the transfer: ‘0b’ for read. LAD
0
is reserved for future implementation.
Address Phase for Memory Cycle: LPC supports 32-bit addressing. It is transferred most
significant nibble first. All the values of A
31
- A
24
must be set to ‘1’. For A
23
- A
20
values,
refer to Table 6.
Turn-Around: Indicates a turn-around cycle to drive LAD
3
- LAD
0
to ‘1111b’ during the
first clock and to drive LAD
3
- LAD
0
to High-Z during the second clock by the host.
Sync: Synchronizes to host or peripheral by adding wait states. ‘0000b’ means Ready,
‘0101b’ means Short Wait. The product supports three types of wait states: ‘no wait’,
‘1-wait’, or ‘2-wait’.
Data Phase: The data byte is transferred least significant nibble first. DQ
3
- DQ
0
on
LAD
3
- LAD
0
first, DQ
7
- DQ
4
on LAD
3
- LAD
0
last.)
Turn-Around: Indicates a turn-around cycle to drive LAD
3
- LAD
0
to ‘1111b’ during the first
clock and to drive LAD
3
- LAD
0
to High-Z during the second clock by the Flash Memory.
ADDR
8
Input
Input
then High-Z
Output
TAR
2
Sync
1-3
Data
TAR
2
2
Output
Output then
High-Z
Table 3. LPC Write Cycle Field Definitions
FIELD
START
CYCTYPE
CLOCKS
1
1
LAD
3
- LAD
0
DIRECTION
Input
Input
DESCRIPTION
Start of Cycle: ‘0000b’ appears on LPC bus to indicate the start.
Cycle Type: Indicates the type of cycle. LAD
3
- LAD
2
must be ‘01b’ for memory cycle.
LAD
1
indicates the direction of the transfer: ‘1b’ for write. LAD
0
is reserved for future
implementation.
Address Phase for Memory Cycle: LPC supports 32-bit addressing. It is transferred
most significant nibble first. All the values of A
31
- A
24
must be set to ‘1’. For A
23
- A
20
values, refer to Table 6.
Data Phase: The data byte is transferred least significant nibble first. DQ
3
- DQ
0
on
LAD
3
- LAD
0
first, DQ
7
- DQ
4
on LAD
3
- LAD
0
last.)
Turn-Around: Indicates a turn-around cycle to drive LAD
3
- LAD
0
to ‘1111b’ during the
first clock and to drive LAD
3
- LAD
0
to High-Z during the second clock by the last com-
ponents driving LAD
3
- LAD
0
.
Sync: This device only supports ‘0000b’ to indicate ready.
Turn-Around: Indicates a turn-around cycle to drive LAD
3
- LAD
0
to ‘1111b’ during the first
clock and to drive LAD
3
- LAD
0
to High-Z during the second clock by the Flash Memory.
ADDR
8
2
2
Input
Data
Input
Input
then High-Z
Output
Output then
High-Z
TAR
Sync
TAR
1
2
4
Data Sheet
8M LPC Flash Memory
LHF00L02
Multi-byte Read (LPC Mode)
This device provides Multi-byte Read operation in
LPC mode. Multi-Byte Read mode enables two or more
byte of sequential data, read at one operation cycle.
This increases data transfer rate compared with normal
memory read operation. The transfer multi-byte size
can be selected from four types.
Table 4. LPC Multi-byte Read Cycle Field Definitions
FIELD
START
CYCTYPE
CLOCKS
1
1
LAD
3
- LAD
0
DIRECTION
Input
Input
DESCRIPTION
Start of Cycle: ‘0000b’ appears on LPC bus to indicate the start of cycle
Cycle Type: ‘1100b’ = Multi-byte Read
Transfer Multi-byte Size for LAD
0
- LAD
1
:
00 = 2 byte
01 = 8 byte
01 = 32 byte
11 = 128 byte
Address: Start address of Multi-byte Read: A
31
- A
0
.
Turn-Around: ‘111b’ and High-Z
Sync:
‘0101b’ = Short Wait
‘0000b’ = Ready
(N = the number of Short Wait)
Data Phase: First byte; DQ
3
- DQ
0
on LAD
3
- LAD
0
(1st cycle)
DQ
7
- DQ
4
on LAD
3
- LAD
0
(2nd cycle)
Sync:
‘0101b’ = Short Wait
‘0000b’ = Ready
(N = the number of Short Wait) (M = number of Multi Byte)
Data Phase: Multi-byte; DQ
3
- DQ
0
on LAD
3
- LAD
0
(1st cycle)
DQ
7
- DQ
4
on LAD
3
- LAD
0
(2nd cycle)
Turn-Around: ‘1111b’ and High-Z
MSIZE
1
Input
ADDR
TAR
8
2
Input
Input then
High-Z
Output
Sync 1
N+1
Data 1
2
Output
Sync M
(N+1) × M
Output
Data M
TAR
2×M
2
Output
Output then
High-Z
Table 5. LPC Multi-byte Read Bandwidth (ƒ(CLK) = 33 MHz)
128-BYTE
MULTI-BYTE READ
START
CYCTYPE
MSIZE+ADDR
TAR
Sync (no-wait)
Data
TAR
Total Clocks
Transfer Time
Bandwidth
CLOCKS
1
1
9
2
1 × 128
2 × 128
2
399
12
10.69
µs
Mbit/s
UNIT
128-BYTE
NORMAL READ
START
CYCTYPE
MSIZE+ADDR
TAR
Sync (no-wait)
Data
TAR
Total Clocks
Transfer Time
Bandwidth
CLOCKS
1 × 128
1 × 128
8 × 128
2 × 128
1 × 128
2 × 128
2 × 128
17 × 128
65
1.96
µs
Mbit/s
UNIT
Data Sheet
5
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