SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002
D
D
D
D
4.5-V to 5.5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 9.5 ns at 5 V
Inputs Are TTL-Voltage Compatible
SN54ACT573 . . . J OR W PACKAGE
SN74ACT573 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in a bus-organized system without need for
interface or pullup components.
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54ACT573 . . . FK PACKAGE
(TOP VIEW)
2D
1D
OE
V
CC
3D
4D
5D
6D
7D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1Q
2Q
3Q
4Q
5Q
6Q
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PDIP − N
SOIC − DW
−40°C to 85°C
40°C
SOP − NS
SSOP − DB
TSSOP − PW
CDIP − J
−55°C to 125 C
55 C 125°C
†
PACKAGE
†
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74ACT573N
SN74ACT573DW
SN74ACT573DWR
SN74ACT573NSR
SN74ACT573DBR
SN74ACT573PWR
SNJ54ACT573J
SNJ54ACT573W
SNJ54ACT573FK
CFP − W
LCCC − FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
8D
GND
LE
8Q
7Q
TOP-SIDE
MARKING
SN74ACT573N
ACT573
ACT573
AD573
AD573
SNJ54ACT573J
SNJ54ACT573W
SNJ54ACT573FK
1
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002
FUNCTION TABLE
(each latch)
INPUTS
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q
0
Z
logic diagram (positive logic)
1
OE
LE
11
C1
1D
2
1D
19
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through, V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±200
mA
Package thermal impedance,
θ
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
†
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002
recommended operating conditions (see Note 3)
SN54ACT573
MIN
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
Δt/Δv
T
A
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−55
0
0
4.5
2
0.8
V
CC
V
CC
−24
24
8
125
−40
0
0
MAX
5.5
SN74ACT573
MIN
4.5
2
0.8
V
CC
V
CC
−24
24
8
85
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
I
OH
= −50
μA
50 A
V
OH
I
OH
= − 24 mA
I
OH
= −50 mA
†
I
OH
= −75 mA
†
I
OL
= 50
μA
A
V
OL
I
OL
= 24 mA
I
OL
= 50 mA
†
I
OL
= 75 mA
†
I
OZ
I
I
I
CC
ΔI
CC‡
C
i
†
‡
V
CC
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
T
A
= 25°C
MIN
4.4
5.4
3.86
4.86
TYP
4.49
5.49
MAX
SN54ACT573
MIN
4.4
5.4
3.7
4.7
3.85
MAX
SN74ACT573
MIN
4.4
5.4
3.76
4.76
V
MAX
UNIT
3.85
0.1
0.1
0.36
0.36
0.1
0.1
0.44
0.44
1.65
1.65
±0.25
±0.1
4
06
0.6
5
±5
±1
80
15
1.5
±2.5
±1
40
15
1.5
μA
μA
μA
mA
pF
0.1
0.1
0.44
0.44
V
V
O
= V
CC
or GND
V
I
= V
CC
or GND
V
I
= V
CC
or GND,
I
O
= 0
One input at 3.4 V,
Other inputs at GND or V
CC
V
I
= V
CC
or GND
5.5 V
55V
5.5
5V
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
CC
.
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
MIN
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
3.5
3
0
MAX
SN54ACT573
MIN
5
4.5
1
MAX
SN74ACT573
MIN
4
3.5
0
MAX
UNIT
ns
ns
ns
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM
(INPUT)
D
LE
OE
OE
TO
(OUTPUT)
Q
Q
Q
Q
T
A
= 25°C
MIN
2.5
2.5
3
2.5
2
1.5
2.5
1.5
TYP
6
6
6
5.5
5.5
5.5
6.5
5
MAX
10.5
10.5
10.5
9.5
10
9.5
11
8.5
SN54ACT573
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
13.5
13.5
13
12
11.5
11
13.5
10.5
SN74ACT573
MIN
2
2
2.5
2
1.5
1.5
1.5
1
MAX
12
12
12
10.5
11
10.5
12.5
9.5
ns
ns
ns
ns
UNIT
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
C
pd
Power dissipation capacitance
TEST CONDITIONS
C
L
= 50 pF,
f = 1 MHz
TYP
25
UNIT
pF
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D − OCTOBER 1995 − REVISED OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
2
×
V
CC
From Output
Under Test
C
L
= 50 pF
(see Note A)
500
Ω
S1
Open
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
2
×
V
CC
Open
500
Ω
3V
Timing Input
LOAD CIRCUIT
t
su
t
w
3V
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
t
PZL
3V
Input
1.5 V
t
PLH
Output
50% V
CC
VOLTAGE WAVEFORMS
1.5 V
0V
t
PHL
V
OH
50% V
CC
V
OL
Output
Waveform 2
S1 at Open
(see Note B)
Output
Waveform 1
S1 at 2
×
V
CC
(see Note B)
t
PZH
50% V
CC
VOLTAGE WAVEFORMS
50% V
CC
3V
1.5 V
1.5 V
0V
t
PLZ
≈V
CC
V
OL
+ 0.3 V
t
PHZ
V
OH
− 0.3 V
V
OH
≈0
V
V
OL
Data Input
1.5 V
1.5 V
t
h
0V
3V
1.5 V
0V
VOLTAGE WAVEFORMS
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, Z
O
= 50
Ω,
t
r
≤
2.5 ns, t
f
≤
2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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5
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