INTEGRATED CIRCUITS
DATA SHEET
SAA7140A; SAA7140B
High Performance Scaler (HPS)
Objective specification
Supersedes data of 1996 Jul 26
File under Integrated Circuits, IC22
1996 Sep 04
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
CONTENTS
1
2
3
4
5
6
7
7.1
7.1.1
7.1.2
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.5
7.6
7.6.1
7.7
7.7.1
7.8
7.8.1
7.8.2
7.8.3
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
9
10
11
12
13
FEATURES
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING (SAA7140A)
PINNING (SAA7140B)
FUNCTIONAL DESCRIPTION
Data format/reformatter and reference signal
generation
Data formats and reference signals of the
DMSD port
Data formats and reference signals of the
expansion port
Acquisition control
BCS control
Scaling unit
Horizontal prescaling
Vertical scaler
Horizontal variable phase scaling
CSM (Colour Space Matrix), dither and gamma
correction
Output formatter and output FIFO register
Data formats and reference signals of the
VRAM port
Data transfer modes
Expansion port modes
VRAM port modes
Data burst transfer mode (FIFO Mode)
Continuous data transfer mode (transparent
mode)
I
2
C-bus controlled pseudo sleep mode
I
2
C-BUS PROTOCOL
I
2
C-bus format
I
2
C-bus bitmap
Description of the I
2
C-bus bits
Initial settings for the expansion and DMSD
port; Subaddress 00H
Initial settings for the VRAM port;
subaddress 01H
Port I/O control; subaddress 21H
Register set A (02H to 1FH) and B
(22H to 3FH)
LIMITING VALUES
HANDLING
THERMAL CHARACTERISTICS
DC CHARACTERISTICS
AC CHARACTERISTICS
2
14
15
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.4
16
17
18
SAA7140A; SAA7140B
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
QFP
SO
Method (QFP and SO)
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
1996 Sep 04
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
1
FEATURES
2
SAA7140A; SAA7140B
GENERAL DESCRIPTION
•
Scaling of video pictures down to randomly sized
windows
•
Horizontal upscaling (zoom)
•
Two dimensional phase-correct data processing for
improved signal quality of scaled data, especially for
compression applications
•
Processing of a maximum of 2047 active samples per
line (V-processing in bypass) and 2047 active lines per
frame
•
16-bit YUV data input port
•
Bidirectional expansion port with full duplex functionality
(D1) or 16-bit YUV input/output
•
Discontinuous data stream supported
•
Field-wise switching between two data sources
•
Two independent I
2
C-bus programming sets
•
Brightness, contrast and saturation controls for scaled
outputs
•
Chroma key (α generation)
•
YUV-to-RGB conversion including anti-gamma
correction for RGB
•
16-word FIFO register for 32-bit output data
•
Output configurable for 32, 24, 16 and 8-bit video data
•
Scaled 16-bit 4 : 2 : 2 YUV output
•
Scaled 15-bit RGB (5, 5, 5) +
α
with dither and 24-bit
RGB (8, 8, 8) +
α
output
•
Scaled 8-bit monochrome output
•
Four independent user configurable general purpose I/O
pins
•
Low power consumption in I
2
C-bus controlled pseudo
sleep mode
•
Support of 5 V (SAA7140A) and pure 3.3 V
(SAA7140B) signalling environment.
3
ORDERING INFORMATION
TYPE
NUMBER
SAA7140A
SAA7140B
The SAA7140A and SAA7140B are CMOS High
Performance Scaler (HPS) and is a highly integrated
circuit designed for use in DeskTop Video (DTV)
applications. The devices resample digital video signals
using two dimensional phase-correct interpolation in order
to display it in an arbitrarily sized window.
The SAA7140A fits perfectly into a 5 V signal environment
and requires two different supply voltages (5 V and 3.3 V).
The SAA7140B is a pure 3.3 V design and therefore has
only 3.3 V supply pins. With respect to functions and
programming, both devices are identical.
The devices incorporate additional functions such as
control of brightness, saturation, contrast, chroma key
generation, YUV-to-RGB conversion, compensation of
gamma precorrection, dithering and choice of several
output formats.
The SAA7140A and SAA7140B accepts data from 1 or 2
input signal sources, via it’s 16-bit YUV input port and/or
the bidirectional expansion port. They deliver scaled data
on the 32-bit VRO output port and, if selected, also on the
bidirectional expansion port. A synchronous (transparent)
together with an asynchronous (burst) data transfer mode
is supported at the 32-bit VRO port.
PACKAGE
NAME
LQFP128
LQFP128
DESCRIPTION
plastic low profile quad flat package; 128 leads; body 14
×
20
×
1.4 mm
plastic low profile quad flat package; 128 leads; body 14
×
20
×
1.4 mm
VERSION
SOT425-1
SOT425-1
1996 Sep 04
3
4
ndbook, full pagewidth
EXPANSION PORT
VIDL7 to 0
LLCIO
PXQIO
HIO
VIO
FDIO
1996 Sep 04
LLCIN
PXQIN
HIN
VIN
VIDH7 to 0
VSSD(core) 1 to 4
VDDD(core) 1 to 4
Philips Semiconductors
BLOCK DIAGRAMS
1
125
126
127
105 to 112
117 to 124
128
104
103
102
97
VDDD(bord) 1 to 12
EXPANSION PORT INTERFACE
VSSD(bord) 1 to 11
SAA7140A
reference
SCALING UNIT
Y
U
V
VERTICAL PROCESSING
YIN7 to 0
Y
Y
U
V
HORIZONTAL
PRESCALING
CONTROL
LINE
MEMORY
ARITHMETIC
HORIZONTAL
FINE
SCALING
UV
18 to 11
DATA
FORMATTER/
REFORMATTER Y
High Performance Scaler (HPS)
UVIN7 to 0
28 to 21
AND
UV
CREF
ACQUISITION
CONTROL
BCS
CONTROL
6
DMSD
PORT
HREF
7
REFERENCE
SIGNAL
GENERATION
PXQ
VS
8
H
4
Y
U
V
B
G
OUTPUT FORMATTER
OUTPUT FIFO REGISTER
R
CSM
DITHERING
γ-CORRECTION
43
44
49
52
50
56
AP
SP
BTST
VMUX
VOEN
VCLK
LLC
5
V
CLK
PORT3 to 0
38 to 41
57 to 65, 70 to 81, 86 to 96
47
46
45
48
55
54
VRO31 to 0
HGTV
VSYV
FLDV
PXQV
INCADR
HFL
SCL
32
controls
I
2
C
SDA
31
CONTROL
status
VRAM
PORT
IICSA
33
RES
42
MHA117
SAA7140A; SAA7140B
Objective specification
Fig.1 Block diagram (SAA7140A).
LLCIN
PXQIN
HIN
VIN
VIDH7 to 0
handbook, full pagewidth
1996 Sep 04
EXPANSION PORT
VIDL7 to 0
LLCIO
PXQIO
HIO
VIO
FDIO
1
125
126
127
105 to 112
117 to 124
128
104
103
102
97
EXPANSION PORT INTERFACE
Philips Semiconductors
VDDD1 to 16
VSSD1 to 15
SAA7140B
reference
SCALING UNIT
Y
U
V
VERTICAL PROCESSING
YIN7 to 0
Y
Y
U
V
HORIZONTAL
PRESCALING
CONTROL
LINE
MEMORY
ARITHMETIC
HORIZONTAL
FINE
SCALING
UV
UV
18 to 11
DATA
FORMATTER/
REFORMATTER Y
High Performance Scaler (HPS)
UVIN7 to 0
28 to 21
AND
CREF
PXQ
H
V
ACQUISITION
CONTROL
BCS
CONTROL
6
DMSD
PORT
HREF
7
REFERENCE
SIGNAL
GENERATION
VS
8
5
Y
U
V
B
G
OUTPUT FORMATTER
OUTPUT FIFO REGISTER
R
CSM
DITHERING
γ-CORRECTION
43
44
49
52
50
56
AP
SP
BTST
VMUX
VOEN
VCLK
LLC
5
CLK
PORT3 to 0
38 to 41
57 to 65, 70 to 81, 86 to 96
47
46
45
48
55
54
VRO31 to 0
HGTV
VSYV
FLDV
PXQV
INCADR
HFL
SCL
32
controls
SDA
31
I
2
C
CONTROL
status
VRAM
PORT
IICSA
33
RES
42
MHA360
SAA7140A; SAA7140B
Objective specification
Fig.2 Block diagram (SAA7140B).
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