INTEGRATED CIRCUITS
DATA SHEET
SAA7126H; SAA7127H
Digital video encoder
Product specification
Supersedes data of 1999 May 31
2002 Oct 15
Philips Semiconductors
Product specification
Digital video encoder
CONTENTS
1
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
8.1
8.2
9
9.1
10
11
11.1
11.2
11.3
11.4
11.5
12
13
14
15
16
FEATURES
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Data manager
Encoder
RGB processor
Output interface/DACs
Synchronization
Clock
I
2
C-bus interface
Input levels and formats
Bit allocation map
I
2
C-bus format
Slave receiver
Slave transmitter
CHARACTERISTICS
Explanation of RTCI data bits
Teletext timing
APPLICATION INFORMATION
Analog output voltages
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
REVISION HISTORY
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
SAA7126H; SAA7127H
2002 Oct 15
2
Philips Semiconductors
Product specification
Digital video encoder
1
FEATURES
SAA7126H; SAA7127H
•
Monolithic CMOS 3.3 V device, 5 V I
2
C-bus optionally
•
Digital PAL/NTSC encoder
•
System pixel frequency 13.5 MHz
•
54 MHz double-speed multiplexed D1 interface capable
of splitting data into two separate channels (encoded
and baseband)
•
Four Digital-to-Analog Converters (DACs) for CVBS
(CSYNC, VBS), RED (C
R
, C), GREEN (Y, VBS) and
BLUE (C
B
, CVBS) two times oversampled (signals in
parenthesis are optionally). RED (C
R
), GREEN (Y) and
BLUE (C
B
) signal outputs with 9-bit resolution, whereas
all other signal outputs have 10-bit resolution; CSYNC is
an advanced composite sync on the CVBS output for
RGB display centring.
•
Real-time control of subcarrier
•
Cross-colour reduction filter
•
Closed captioning encoding and World Standard
Teletext (WST) and North-American Broadcast Text
System (NABTS) teletext encoding including sequencer
and filter
•
Copy Generation Management System (CGMS)
encoding (CGMS described by standard CPR-1204 of
EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via
the I
2
C-bus
•
Fast I
2
C-bus control port (400 kHz)
•
Line 23 Wide Screen Signalling (WSS) encoding
•
Video Programming System (VPS) data encoding in
line 16 (CCIR line count)
•
Encoder can be master or slave
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
•
Internal Colour Bar Generator (CBG)
•
Macrovision™
(1)
Pay-per-View copy protection system
rev. 7.01 and rev. 6.1 as option; ‘handsfree’ Macrovision
pulse support through on-chip timer for pulse amplitude
modulation; this applies to SAA7126H only. The device
is protected by USA patent numbers 4631603, 4577216
and 4819098 and other intellectual property rights. Use
of the Macrovision anti-copy process in the device is
licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information
•
Controlled rise/fall times of output syncs and blanking
•
On-chip crystal oscillator (3rd-harmonic or fundamental
crystal)
•
Down mode (low output voltage) or power-save mode of
DACs
•
QFP44 package.
2
GENERAL DESCRIPTION
The SAA7126H; SAA7127H encodes digital C
B
-Y-C
R
video data to an NTSC or PAL CVBS or S-video signal.
Simultaneously, RGB or bypassed but interpolated
C
B
-Y-C
R
signals are available via three additional
Digital-to-Analog Converters (DACs). The circuit at a
54 MHz multiplexed digital D1 input port accepts two CCIR
compatible C
B
-Y-C
R
data streams with 720 active pixels
per line in 4 : 2 : 2 multiplexed formats, for example MPEG
decoded data with overlay and MPEG decoded data
without overlay, whereas one data stream is latched at the
rising, the other one at the falling clock edge.
It includes a sync/clock generator and on-chip DACs.
(1) Macrovision™ is a trademark of the Macrovision Corporation.
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7126H
SAA7127H
QFP44
DESCRIPTION
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
VERSION
SOT307-2
2002 Oct 15
3
Philips Semiconductors
Product specification
Digital video encoder
4
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
V
i
V
o(p-p)
R
L
LE
lf(i)
LE
lf(d)
T
amb
5
PARAMETER
analog supply voltage
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
analog output signal voltages Y, C and CVBS
without load (peak-to-peak value)
load resistance
low frequency integral linearity error
low frequency differential linearity error
ambient temperature
1.30
75
−
−
0
SAA7126H; SAA7127H
MIN.
3.15
3.0
−
−
TYP.
3.3
3.3
77
37
1.45
−
−
−
−
MAX.
3.45
3.6
100
46
1.55
300
±3
±1
70
V
V
UNIT
mA
mA
V
Ω
LSB
LSB
°C
TTL compatible
BLOCK DIAGRAM
handbook, full pagewidth
XTALI
RESET SDA SCL
40
42
41
RCV1
TTXRQ
LLC1
VDDA2 VDDA4
VDDA1 VDDA3
XTAL
35
34
7
RCV2
8
XCLK
43
37
4
25 28
31 36
VDD(I2C)
SA
RES
20
21
1
I
2
C-bus
control
I
2
C-BUS
INTERFACE
I
2
C-bus
control
SYNC/CLOCK
I
2
C-bus
control
I
2
C-bus
control
Y
ENCODER
C
OUTPUT
INTERFACE
D
30
CVBS
SAA7126H
SAA7127H
Y
clock
and timing
MP7
to
MP0
9 to 16
MP1
MP2
DATA
MANAGER
CB
−C
R
23
TTX
44
I
2
C-bus
control
Y
n.c.
24, 27
CB
−C
R
RGB
PROCESSOR
29
A
I C-bus
control
2
RED
GREEN
BLUE
26
5
VSSD1
18
38
6
VDDD1
17
39
19
RTCI
2
SP
3
AP
22
VSSA1
32
33
VSSD3
VDDD3
VSSA3
MHB498
VSSD2
VDDD2
VSSA2
Fig.1 Block diagram.
2002 Oct 15
4
Philips Semiconductors
Product specification
Digital video encoder
6
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TYPE
−
I
I
I
supply
supply
I/O
I/O
I
I
I
I
I
I
I
I
supply
supply
I
digital supply voltage 2
digital ground 2
reserved pin; do not connect
SAA7126H; SAA7127H
SYMBOL
RES
SP
AP
LLC1
V
SSD1
V
DDD1
RCV1
RCV2
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
V
DDD2
V
SSD2
RTCI
DESCRIPTION
test pin; connected to digital ground for normal operation
test pin; connected to digital ground for normal operation
line-locked clock input; this is the 27 MHz master clock
digital ground 1
digital supply voltage 1
raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal
raster control 2 for video port; this pin provides an HS pulse of programmable
length or receives an HS pulse
double-speed 54 MHz MPEG port; it is an input for
“CCIR 656”
style multiplexed
C
B
-Y-C
R
data; data is sampled on the rising and falling clock edge; data sampled
on the rising edge is then sent to the encoding part of the device; data sampled on
the falling edge is sent to the RGB part of the device (or vice versa, depending on
programming)
real-time control input (I
2
C-bus register SRES = 0): if the LLC1 clock is provided by
an SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the
respective decoder to improve the signal quality. Sync reset input (I
2
C-bus register
SRES = 1): a HIGH impulse resets synchronization of the encoder (first field, first
line).
sense input for I
2
C-bus voltage; connect to I
2
C-bus supply
select I
2
C-bus address; LOW selects slave address 88H, HIGH selects slave
address 8CH
analog ground 1 for RED (C
R
) (C) and GREEN (Y) (VBS) outputs
analog output of RED (C
R
) or (C) signal
not connected
analog supply voltage 1 for RED (C
R
) (C) output
analog output of GREEN (Y) or (VBS) signal
not connected
analog supply voltage 2 for GREEN (Y) (VBS) output
analog output of BLUE (C
B
) or (CVBS) signal
analog output of CVBS (CSYNC) or (VBS) signal
analog supply voltage 3 for BLUE (C
B
) (CVBS) and CVBS (CSYNC) (VBS) outputs
analog ground 2 for BLUE (C
B
) (CVBS) and CVBS (CSYNC) (VBS) outputs
analog ground 3 for the DAC reference ladder and the oscillator
crystal oscillator output
V
DD(I2C)
SA
V
SSA1
RED
n.c.
V
DDA1
GREEN
n.c.
V
DDA2
BLUE
CVBS
V
DDA3
V
SSA2
V
SSA3
XTAL
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
supply
I
supply
O
−
supply
O
−
supply
O
O
supply
supply
supply
O
2002 Oct 15
5
嵌入式系统
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