Si9410DY
N-channel TrenchMOS ™ logic level FET
M3D315
Rev. 03 — 23 January 2004
Product data
1. Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
2. Features
s
Low on-state resistance
s
Fast switching
3. Applications
s
s
s
s
s
DC-to-DC converters
DC motor control
Lithium-ion battery applications
Notebook PC
Portable equipment applications.
4. Pinning information
Table 1:
Pin
1
2,3
4
5,6,7,8
Pinning - SOT96-1 (SO8), simplified outline and symbol
Description
n/c
8
5
d
Simplified outline
Symbol
source (s)
gate (g)
drain (d)
1
Top view
4
MBK187
g
s
MBB076
SOT96-1 (SO8)
Philips Semiconductors
Si9410DY
N-channel TrenchMOS ™ logic level FET
5. Quick reference data
Table 2:
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Conditions
25
°C ≤
T
j
≤
150
°C
T
amb
= 25
°C;
pulsed; t
p
≤
10 s
T
amb
= 25
°C;
pulsed; t
p
≤
10 s
V
GS
= 10 V; I
D
= 7 A
V
GS
= 5 V; I
D
= 4 A
V
GS
= 4.5 V; I
D
= 3.5 A
Typ
-
-
-
-
19
23
25
Max
30
7
2.5
150
30
40
50
Unit
V
A
W
°C
mΩ
mΩ
mΩ
drain-source voltage (DC)
drain current (DC)
total power dissipation
junction temperature
drain-source on-state resistance
Symbol Parameter
6. Ordering information
Table 3:
Ordering information
Package
Name
Si9410DY
SO8
Description
Plastic small outline package; 8 leads
Version
SOT96-1
Type number
7. Limiting values
Table 4: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
amb
= 25
°C;
pulsed: t
p
≤
10 s
T
amb
= 25
°C;
pulsed; t
p
≤
10 s;
Figure 2
and
3
T
amb
= 70
°C;
pulsed; t
p
≤
10 s;
Figure 2
T
amb
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
amb
= 25
°C;
pulsed; t
p
≤
10 s;
Figure 1
T
amb
= 70
°C;
pulsed; t
p
≤
10 s;
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
Min
-
-
-
-
-
-
-
−55
−55
-
Max
30
±20
7
5.8
20.8
2.5
1.6
+150
+150
2.3
Unit
V
V
A
A
A
W
W
°C
°C
A
Source-drain diode
9397 750 12542
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 23 January 2004
2 of 12
Philips Semiconductors
Si9410DY
N-channel TrenchMOS ™ logic level FET
120
Pder
(%)
80
03aa11
120
Ider
(%)
80
03aa19
40
40
0
0
50
100
150
200
Tamb (
°
C)
0
0
50
100
150
200
Tamb (
°
C)
P
tot
P
der
=
----------------------
×
100%
P
°
tot
(
25 C
)
V
GS
≥
10 V
I
D
I
D
=
------------------
×
100%
-
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of ambient temperature.
Fig 2. Normalized continuous drain current as a
function of ambient temperature.
102
ID
(A)
10
Limit RDSon = VDS /ID
tp = 10
µ
s
03ae46
1 ms
1
100 ms
DC
1s
10-1
10 s
10-2
10-1
1
10
VDS (V)
102
T
amb
= 25
°C;
I
DM
is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 12542
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 23 January 2004
3 of 12
Philips Semiconductors
Si9410DY
N-channel TrenchMOS ™ logic level FET
8. Thermal characteristics
Table 5:
R
th(j-a)
Thermal characteristics
Conditions
mounted on a printed-circuit board;
minimum footprint, t
p
≤
10 s;
Figure 4
Min Typ Max Unit
-
-
50
K/W
thermal resistance from junction to ambient
Symbol Parameter
8.1 Transient thermal impedance
102
Zth(j-a)
(K/W)
0.2
10
0.1
0.05
0.02
1
P
δ
= 0.5
03ae45
δ
=
tp
T
single pulse
10-1
10-5
tp
T
t
10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration.
9397 750 12542
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 23 January 2004
4 of 12
Philips Semiconductors
Si9410DY
N-channel TrenchMOS ™ logic level FET
9. Characteristics
Table 6: Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
GS(th)
I
DSS
gate-source threshold voltage
drain-source leakage current
I
D
= 250
µA;
V
DS
= V
GS
;
Figure 9
V
DS
= 24 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 55
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±20
V; V
DS
= 0 V
V
GS
= 10 V; I
D
= 7 A;
Figure 7
and
8
V
GS
= 5 V; I
D
= 4 A;
Figure 8
V
GS
= 4.5 V; I
D
= 3.5 A;
Figure 7
and
8
Dynamic characteristics
g
fs
Q
g(tot)
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
forward transconductance
total gate charge
gate-source charge
gate-drain (Miller) charge
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 2 A; V
GS
= 0 V;
Figure 12
reverse recovery time
I
S
= 2 A; dI
S
/dt =
−100
A/µs; V
GS
= 0 V
V
DD
= 25 V; R
D
= 25
Ω;
V
GS
= 10 V; R
G
= 6
Ω
V
DS
= 15 V; I
D
= 7 A
I
D
= 7 A; V
DS
= 15 V; V
GS
= 10 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
15
14.6
2
3
5
6
21
11
0.85
30
-
50
-
-
30
60
150
140
1.1
-
S
nC
nC
nC
ns
ns
ns
ns
V
ns
-
-
-
-
-
-
-
-
-
19
23
25
2
25
100
30
40
50
µA
µA
nA
mΩ
mΩ
mΩ
1
-
-
V
Conditions
Min
Typ
Max
Unit
Source-drain (reverse) diode
9397 750 12542
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 23 January 2004
5 of 12
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