HD66130T
320-channel Low-voltage Segment Driver for Dot-Matrix STN
Liquid Crystal Display
Description
The HD66130T is a 320-channel segment driver for driving a dot-matrix STN liquid-crystal panel at a low
voltage. The driver can also correspond to 240-channel output by switching mode. It operates at a low
voltage: a liquid-crystal drive voltage of 5 V and a logic drive voltage of 3 V, and is used together with
common driver HD66131T or HD66135T. The package, which adopts a flexible TCP, can be applied to
various liquid crystal panels.
Features
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Display duty: Up to 1/240
Liquid crystal drive voltage: 2.6 to 5.5 V
Number of liquid crystal drive circuits: 320 circuits
Operating voltage: 2.5 to 5.5 V
Number of data bits: 4 or 8 bits
Shift clock speed: 8 MHz max/5V
6.5 MHz max/3V
Together with the common drivers
HD66131T , HD66135T
Low power consumption
Switching output mode: 320 output mode
240 output mode
Display-off function
Flexible TCP
Automatic generation of chip-enable signals
Standby function
1
HD66130T
Pin Arrangement
316 Y316
317 Y317
318 Y318
319 Y319
Y320
320
V0L
VML
V1L
Y1
1
2 Y2
3 Y3
4 Y4
5 Y5
Top View
Note: TCP dimensions are not defined.
Internal Block Diagram
Y
1
–Y
320
V0L
VML
V1L
VML
V0L
V1L
V
CC
MODE
BS
GND2
SHL
EIO1
DISP
D0
D1
D2
D3
D4
D5
D6
D7
CL2
CL1
M
EIO2
GND1
V1R
V0R
VMR
346
345
344
343
342
341
340
339
338
337
336
335
334
333
332
331
330
329
328
327
326
325
324
323
322
321
*
Liquid crystal drive circuit
Vcc
GND2
GND1
CL1
M
BS
Data
rearrangement
circuit
Timing
generator
circuit
Level shifter
Level
shifter
Latch circuit 2
DISP
Latch circuit 1
Latch circuit 1
D0–D7
SHL
MODE
CL2
Shift register
EIO1
EIO2
Note: Pins V0L, VML, and V1L are internally connected to pins V0R, VMR, and V1R, respectively.
2
HD66130T
1. Liquid crystal drive circuit
Selects and outputs the liquid crystal drive level V0, VM, or V1 by
DISP
and a combination of data for
latch circuit 2 and signal M.
2. Level shifter
Converts logic signals to liquid crystal drive signals.
3. Latch circuit 2
320-bit latch circuit, which latches the data of latch circuits 1 at the fall of CL1 and outputs the data to
the level shifter.
4. Latch circuit 1
4/8-bit parallel data latch circuit, which latches display data D0 to D7 according to signals transmitted
from the shift register.
5. Shift register
80-bit shift register, which generates data-capture signals for latch circuits 1 at the fall of CL2.
6. Data rearrangement circuit
Inverts the order of data output crosswise.
7. Timing generator circuit
The timing generator circuit generates data latch pulses for latch circuit2 and changes pulse the LCD
drive outputs to AC.
HIFAS Family timing Comparision
HD66130/131/134/135
Input
signal
CL1
M
Segment
Common
HD66132/133
Output
signal
3
HD66130T
Pin Functions
Class
Power
supply
Pin
Pin
Symbol Number Name
V
CC
GND1
GND2
343
324
340
V
CC
GND
I/O
—
Functions
V
CC
–GND: Power supply for logic.
V0L, R 345, 322 V0L, R
VML, R 346, 321 VML, R
V1L, R 344, 323 V1L, R
Input Liquid crystal drive level power supply
V0
VM
V1
Input Latch signal of display data: A liquid crystal drive signal
corresponding to display data is output at the fall of CL1.
Input Capture signal of display data: Display data is captured
at the fall of CL2.
Input A.C. signal of liquid crystal drive output
Display data Liquid crystal drive output Liquid crystal display
1 (Vcc level)
Selected level
ON
OFF
Control
signal
CL1
CL2
M
327
328
326
Clock 1
Clock 2
M
D0 to D7 336 to
329
DATA 0 Input
to
DATA 7
0 (GND level) Not-selected level
SHL
EIO1
339
338
Shift Left Input Control signal for inverting the order of data output
(see the following page)
Enable
IO1
I/O
SHL
GND
Vcc
EI/O1
Enable input
Enable output
EI/O2
Enable output
Enable input
EIO2
325
Enable
IO2
I/O
Enable input: The enable input of the first IC is
connected to the GND and another is connected to the
enable output of the second IC.
Enable output: Connected to the enable input of the
second IC at cascade output.
DISP
BS
337
341
Disp off
Bus
Select
Input Grounding
DISP
sets liquid crystal drive output Y1–Y320
to the VM level.
Input Switches the number of input bits for the display data.
Vcc
8-bit input mode
GND 4-bit input mode (Captures data from D0–D3. At this
time, connect D4–D7 to the GND.)
MODE
342
MODE
Input Switches the number of input bits for the display data.
Vcc
GND
320 output mode
240 output mode (Y41–Y280 are valid output. The
other 80 pins output the not-selected-level signals
synchronized every time; release these pins.)
4
HD66130T
Pin Functions (cont)
Class
Pin
Pin
Symbol Number Name
1 to 320 Y1 to
Y320
I/O
Function
Liquid crystal Y1 to
drive output Y320
Output Liquid crystal drive output: Selects and outputs level
V0 or V1 according to the combination of the M signal
and display data when
DISP
is connected to Vcc.
M
D
Output level
1
V0
1
0
V1
1
V1
0
0
V0
5
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