Freescale Semiconductor
Data Sheet: Advance Information
Document Number: IMX53AEC
Rev. 1, 3/2011
MCIMX53xA
This document contains information on a new
product. Specifications and information herein
are subject to change without notice.
i.MX53xA Automotive
and Infotainment
Applications
Processors
1
Introduction
1.
Package Information
Plastic Package
Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch
Ordering Information
See
Table 1 on page 3
The MCIMX53xA (i.MX53xA) automotive
infotainment processor is Freescale Semiconductor’s
latest addition to a growing family of
multimedia-focused products offering high performance
processing with a high degree of functional integration
aimed at the growing automotive infotainment,
telematics, HMI, and display-based cluster markets. This
device includes 3D and 2D graphics processors, 1080i/p
video processing, and dual display, and provides a
variety of interfaces.
The i.MX53xA processor features Freescale’s advanced
implementation of the ARM™ core, which operates at
clock speeds as high as 800 MHz and interfaces with
DDR2/LVDDR2-800, LPDDR2-800, or DDR3-800
DRAM memories. This device is well-suited for
graphics rendering for HMI and navigation, high
performance speech processing with large databases,
video processing and display, audio playback, and many
other applications.
The flexibility of the i.MX53xA architecture allows for
its use in a wide variety of applications. As the heart of
the application chipset, the i.MX53xA processor
2.
3.
4.
5.
6.
7.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1. Special Signal Considerations . . . . . . . . . . . . . . . 17
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 17
4.2. Power Supplies Requirements and Restrictions . 24
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4. Output Buffer Impedance Characteristics . . . . . . 34
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36
4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 43
4.7. External Peripheral Interfaces Parameters . . . . . . 64
4.8. XTAL and CKIL Electricals . . . . . . . . . . . . . . . . . 151
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 152
5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 152
5.2. Boot Devices Interfaces Allocation . . . . . . . . . . . 153
5.3. Power setup during Boot . . . . . . . . . . . . . . . . . . 154
Package Information and Contact Assignments . . . . . 155
6.1. 19x19 mm Package Information . . . . . . . . . . . . . 155
6.2. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 174
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© 2011 Freescale Semiconductor, Inc. All rights reserved.
Introduction
provides all the interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive,
camera sensors, and dual displays.
Features of the i.MX53xA processor include the following:
• Multilevel memory system—The multilevel memory system of the i.MX53xA is based on the L1
instruction and data caches, L2 cache, internal and external memory. The i.MX53xA supports
many types of external memory devices, including DDR2, low voltage DDR2, LPDDR2, DDR3,
NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed
NAND including eMMC up to rev 4.4.
• Smart speed technology—The i.MX53xA device has power management throughout the IC that
enables the rich suite of multimedia features and peripherals to consume minimum power in both
active and various low power modes. Smart Speed Technology enables the designer to deliver a
feature-rich product requiring levels of power far lower than industry expectations.
• Multimedia powerhouse—The multimedia performance of the i.MX53xA processor ARM core is
boosted by a multilevel cache system, Neon (including advanced SIMD, 32-bit single-precision
floating point support) and vector floating point coprocessors. The system is further enhanced by
a multistandard hardware video codec, autonomous image processing unit (IPU), and a
programmable smart DMA (SDMA) controller.
• Powerful graphics acceleration— The i.MX53xA processors provide two independent, integrated
graphics processing units: an OpenGL
®
ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s,
and 800 Mpix/s z-plane performance) and an OpenVG™ 1.1 2D graphics accelerator
(200 Mpix/s).
• Interface flexibility—The i.MX53xA processor supports connection to a variety of interfaces,
including LCD controller for two displays and CMOS sensor interface, high-speed USB on-the-go
with PHY, plus three high-speed USB hosts, multiple expansion card ports (high-speed
MMC/SDIO host and other), 10/100 Ethernet controller, and a variety of other popular interfaces
(PATA, UART, I
2
C, and I
2
S serial audio, among others).
• Automotive environment support—Includes interfaces such as two CAN ports, an MLB port, an
ESAI audio interface, and an asynchronous sample rate converter for multichannel/multisource
audio.
• Advanced security—The i.MX53xA processors deliver hardware-enabled security features that
enable secure e-commerce, digital rights management (DRM), information encryption, secure
boot, and secure software downloads. For detailed information about the i.MX53xA security
features contact a Freescale representative.
The i.MX53xA application processor is a follow-on to the i.MX51xA, with improved performance, power
efficiency, and multimedia capabilities.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
2
Freescale Semiconductor
Introduction
1.1
Ordering Information
Table 1. Ordering Information
Part Number
Mask
Set
N78C
Features
800 MHz, full feature set
—
Package
1
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
Table 1
provides ordering information.
PCIMX536AVV8B
1
Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.
1.2
Features
The i.MX53xA multimedia applications processor (AP) is based on the ARM Platform, which has the
following features:
• MMU, L1 instruction and L1 data cache
• Unified L2 cache
• Target frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz
• Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)
coprocessor supporting VFPv3
• TrustZone
The memory system consists of the following components:
• Level 1 cache:
— Instruction (32 Kbyte)
— Data (32 Kbyte)
• Level 2 cache:
— Unified instruction and data (256 Kbyte)
• Level 2 (internal) memory:
— Boot ROM, including HAB (64 Kbyte)
— Internal multimedia/shared, fast access RAM (128 Kbyte)
— Secure/non-secure RAM (16 Kbyte)
• External memory interfaces:
— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte
— 32bit LPDDR2
— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC
— 8,16-bit NOR Flash, PSRAM & cellular RAM.
— 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.
— 8-bit Asynchronous (DTACK mode) EIM interface.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Freescale Semiconductor
3
Introduction
— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects
EIM port, as primary muxing at system boot.
— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O
mode)
The i.MX53xA system is built around the following system on chip interfaces:
• 64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU,
GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.
• 32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.
• 32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral
devices operating at 66 MHz.
The i.MX53xA makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia
performance. The use of hardware accelerators provides both high performance and low power
consumption while freeing up the CPU core for other tasks.
The i.MX53xA incorporates the following hardware accelerators:
• VPU, version 3—video processing unit
• GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and
800 Mpix/s z-plane performance, 256 Kbyte RAM memory
• GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,
• IPU, version 3M—image processing unit
• ASRC—asynchronous sample rate converter
The i.MX53xA includes the following interfaces to external devices:
NOTE
Not all interfaces are available simultaneously, depending on I/O
multiplexer configuration.
•
Hard disk drives:
— PATA, up to U-DMA mode 5, 100 MByte/s
— SATA I, 1.5 Gbps
Displays:
— Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two
interfaces may be active at once.
— Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example,
UXGA @ 60 Hz).
— LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel
ports up to 85 MP/s (for example, WXGA @ 60 Hz) each.
— TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).
Camera sensors:
— Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up
to 120-MHz peak clock frequency.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
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Freescale Semiconductor
•
•
Introduction
•
•
•
•
Expansion cards:
— Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port
supporting 832 Mbps (8-bit, eMMC 4.4).
USB
— High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY
— Three USB 2.0 (480 Mbps) hosts:
– High-speed host with integrated on-chip high-speed PHY
– Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB
Automotive environment interfaces:
— Two controller area network (FlexCAN) interfaces, 1 Mbps each
— Media local bus or MediaLB (MLB) provides interface to most networks (50 Mbps)
— Enhanced serial audio interface (ESAI), up to 1.4 Mbps each channel
Miscellaneous interfaces:
— One-wire (OWIRE) port
— Three I2S/SSI/AC97ports, supporting up to 1.4 Mbps, each connected to audio multiplexer
(AUDMUX) providing four external ports.
— Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support
4-wire.
— Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port
— Three I
2
C ports, supporting 400 kbps
— Fast Ethernet controller, IEEE1588 V1 compliant, 10/100 Mbps
— Sony Phillips Digital Interface (SPDIF), Rx and Tx
— Key pad port (KPP)
— Two pulse-width modulators (PWM)
— GPIO with interrupt capabilities
— Secure JTAG controller (SJC)
The system supports efficient and smart power control and clocking:
• Power gating SRPG (State Retention Power Gating) for ARM core and Neon
• Support for various levels of system power modes
• Flexible clock gating control scheme
• On-chip temperature monitor
• On-chip oscillator amplifier supporting 32.768 kHz external crystal
• On-chip LDO voltage regulators for PLLs
Security functions are enabled and accelerated by the following hardware:
•
ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so
on)
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Freescale Semiconductor
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