HV4937
64-Channel Serial To Parallel Converter
With P-Channel Open Drain Outputs
Ordering Information
Package Options
Device
HV4937
80-Lead Quad
Plastic Gullwing
HV4937PG
Die
HV4937X
Features
s
HVCMOS
®
Technology
s
Output voltages up to -375V
s
Source current minimum 0.25mA
s
Shift register speed 6 MHz
s
Latched outputs
s
CMOS compatible inputs
s
Forward and reverse shifting options
General Description
Not recommended for new designs.
The HV49 is a low voltage serial to high voltage parallel converter
with open drain outputs. It has been designed especially for use
as a driver for electrostatic printers.
This device consists of a 64-bit shift register, 64 latches, a latch
enable (LE), and an output enable (OE). Data is shifted through
the shift register on the high to low transition of the clock. When
the DIR pin is set high, the HV49 shifts in the counterclockwise
direction when viewed from the top of the package. When the DIR
pin is set low, the HV49 shifts in the clockwise direction. A serial
data output buffer is provided for cascading devices. This output
reflects the current status of the last bit of the shift register.
Operation of the shift register is not affected by the LE or the OE
inputs. Transfer of data from the shift register to the latch occurs
when the LE input is high. The data in the latch is stored when LE
is low.
12
Absolute Maximum Ratings
1
Supply voltage, V
DD
Supply voltage, V
PP
Logic input levels
Ground current
Continuous total power dissipation
2
Operating temperature range
Storage temperature range
+0.5V to -9V
+0.5V to -400V
+0.5V to V
DD
-0.5V
0.75A
1200mW
-40°C to +85°C
-65°C to +150°C
Notes:
1. All voltages are referenced to V
SS
.
2. For operation above 25°C ambient derate linearly by 20mW/°C up to 85°C.
12-29
HV4937
Electrical Characteristics
(over recommended operating conditions unless noted)
DC Characteristics
Symbol
I
DD
I
DDQ
I
O(OFF)
I
IH
I
IL
V
OH
V
OL
V
OC
C
HVO
Parameter
V
DD
Supply Current
Quiescent V
DD
Supply Current
Off State Output Current at 25°C, per Switch
High-Level Logic Input Current
Low-Level Logic Input Current
High-Level Data Out
Low-Level Output
HV
OUT
Data Out
HV
OUT
Clamp Voltage
Output Capacitance per Channel
-10
-1
-3.0
3
Min
Typ
Max
-15
Units
mA
µA
nA
µA
µA
V
V
V
V
pF
Conditions
f
CLK
= 6MHz, f
DATA
= 3MHz
LE = LOW
-250
-100
-10
+10
V
DD
+1
All V
IN
= 0V
Output high, and at -375V
V
IH
= V
DD
V
I
= 0V
ID
OUT
= -100µA
IHV
OUT
= -0.25mA
ID
OUT
= 100µA
I
OL
= 1mA
V
DS
= 100V
AC Characteristics
Symbol
f
CLK
t
W
t
SU
t
H
t
WLE
t
DLE
t
SLE
t
DHL
t
DLH
(For V
DD
= -5V, T
A
= 25°C)
Parameter
Clock Frequency
Clock Width High or Low
Data Setup Time Before Clock Falls
Data Hold Time After Clock Falls
Width of Latch Enable Pulse
LE Delay Time After Falling Edge of Clock
LE Setup Time Before Falling Edge of Clock
Clock Delay Time Data High to Low
Clock Delay Time Data Low to High
Min
Typ
Max
6
Units
MHz
ns
ns
ns
ns
ns
ns
Conditions
83
35
15
83
35
40
160
160
ns
ns
Recommended Operating Conditions
Symbol
V
DD
HV
OUT
V
IH
V
IL
T
A
Logic supply voltage
High voltage output
High-level input voltage
Low-level input voltage
Operating free-air temperature
Parameter
Min
-4.5
+0.3
-3.5
0
-40
Typ
-5.0
Max
-5.5
-375
V
DD
-0.8
+85
Units
V
V
V
V
°C
Notes:
All voltages are referenced to V
SS.
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
PP
.
Power-down sequence should be the reverse of the above.
12-30
HV4937
Input and Output Equivalent Circuit
V
SS
V
SS
V
SS
Input
Data Out
HV
IN
HV
OUT
V
DD
Logic Inputs
V
DD
Logic Data Output
High Voltage Output
Switching Waveforms
V
IH
Data
In
Data Valid 1
t
SU
Clock
V
IL
Data
Out
t
WH
t
WL
t
H
V
IH
Data Valid 2
V
IL
V
OL
t
DHL
V
OH
Data
Out
t
DLH
V
IH
V
IL
t
DLE
t
WLE
t
SLE
Latch Enable
12-31
HV4937
Functional Block Diagram
V
SS
Output Enable
Latch Enable
Data Input
HV
OUT
1
Clock
HV
OUT
2
64 bit
Static Shift
Register
64 Latches
•
•
•
60 Additional
Outputs
•
•
•
HV
OUT
63
DIR
HV
OUT
64
Data Out
Function Table
Inputs
Function
All off
Load S/R
Data
X
H or L
H or L
Load Latch
Output Enable
Transparent Latch
Mode
H or L
X
H
L
CLK
X
↓
↓
↓
H or L
↓
↓
LE
X
L
L
H
H
H
H
OE
L
L
L
L
H
H
H
DIR
X
H
L
X
X
X
X
Shift Reg
1 2
…
64
*…*
H or L…Qn
→
Qn+1
H or L…Qn
→
Qn-1
H or L…*
H or L…*
H…*
L
…*
Outputs
Latch
HV
OUT
1 2
…
64 1 2
…
64
*…*
*…*
*…*
H or L…*
H or L…*
H…*
L…*
H…H
H…H
H…H
H…H
L or H…*
L
…*
H…*
D
OUT
*
*
*
*
*
*
*
Notes:
X = Don’t care
* = Dependent on previous stage’s state before the last CLK : High to low transition.
↓
= -5V to V
SS
transition
H = V
DD
L = V
SS
12-32
HV4937
Pin Configurations
PG Package
HV49
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Function
V
SS
N/C
HV
OUT
59/6
HV
OUT
60/5
HV
OUT
61/4
HV
OUT
62/3
HV
OUT
63/2
HV
OUT
64/1
DIR
Data Out
CLK
V
SS
V
DD
LE
Data In
OE
HV
OUT
1/64
HV
OUT
2/63
HV
OUT
3/62
HV
OUT
4/61
HV
OUT
5/60
HV
OUT
6/59
N/C
V
SS
HV
OUT
7/58
HV
OUT
8/57
HV
OUT
9/56
HV
OUT
10/55
HV
OUT
11/54
HV
OUT
12/53
HV
OUT
13/52
HV
OUT
14/51
HV
OUT
15/50
HV
OUT
16/49
HV
OUT
17/48
HV
OUT
18/47
HV
OUT
19/46
HV
OUT
20/45
HV
OUT
21/44
HV
OUT
22/43
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Function
N/C
N/C
HV
OUT
23/42
HV
OUT
24/41
HV
OUT
25/40
HV
OUT
26/39
HV
OUT
27/38
HV
OUT
28/37
HV
OUT
29/36
HV
OUT
30/35
HV
OUT
31/34
HV
OUT
32/33
HV
OUT
33/32
HV
OUT
34/31
HV
OUT
35/30
HV
OUT
36/29
HV
OUT
37/28
HV
OUT
38/27
HV
OUT
39/26
HV
OUT
40/25
HV
OUT
41/24
HV
OUT
42/23
N/C
N/C
HV
OUT
43/22
HV
OUT
44/21
HV
OUT
45/20
HV
OUT
46/19
HV
OUT
47/18
HV
OUT
48/17
HV
OUT
49/16
HV
OUT
50/15
HV
OUT
51/14
HV
OUT
52/13
HV
OUT
53/12
HV
OUT
54/11
HV
OUT
55/10
HV
OUT
56/9
HV
OUT
57/8
HV
OUT
58/7
Package Outline
64
65
41
40
Index
80
1
top view
80-pin Gullwing Package
24
25
Note:
Pin designation DIR = H or L
Example: For DIR = H, Pin 3 is HV
OUT
59
For DIR = L, Pin 3 is HV
OUT
6
12-33
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