TSC21020F
Radiation Tolerant 32/40–Bit IEEE Floating–Point
DSP Microprocessor
Introduction
TEMIC Semiconductors is manufacturing a radiation
tolerant version of the Analog Devices ADSP–21020
32/40–Bit Floating–Point DSP.
The product is pin and code compatible with ADI
product, making system development straight forward
and cost effective, using existing development tools and
algorithms.
Features
D
Superscalar IEEE Floating-Point-Processor
D
Off-Chip Harvard Architecture Maximizes Signal Processing
Performance
D
50 ns, 20 MIPS Instruction Rate, Single-Cycle Execution
D
60 MFLOPS Peak, 40 MFLOPS Sustained Performance
D
1024-Point Complex FFT Benchmark : 0.975 ms
D
Divide (y/x) : 300 ns
D
Inverse Square Root (1/√x) : 450 ns
D
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats
D
32-Bit Fixed-Point Formats, Integer and Fractional, with
80-Bit Accumulators
D
IEEE Exception Handling with Interrupt on Exception
D
Three Independent Computation Units : Multiplier, ALU,
and Barrel Shifter
D
Dual Data Address Generators with Indirect, Immediate,
Modulo, and Bit Reverse Addressing Modes
D
Two Off-Chip Memory Transfers in Parallel with Instruction
Fetch and Single-Cycle Multiply & ALU Operations
D
Multiply with Add & Subtract for FFT Butterfly
Computation
D
Efficient Program Sequencing with Zero-Overhead
Looping : Single-Cycle Loop Setup
D
Single-Cycle Register File Context Switch
D
23 ns External RAM Access Time for Zero-Wait-State, 40 ns
Instruction Execution
D
IEEE JTAG Standard 1149.1 Test Access Port and On-Chip
Emulation Circuitry
D
223 CPGA package for breadboarding
D
256 Multi layer quad flat pack, flat leads, for flight models
D
Full compatible with Analog Devices ADSP-21020
D
Latch up immune
D
Total dose better than 100 Krad (Si)
D
SEU immunity better than 50 MeV/mg/cm
2
D
For 25 MHz specification, call factory
– Design using patent from INPG–CNRS Denis BESSOT / Raoul VELAZCO
– Product licensed from Analog Devices Inc.
1
Rev. E – Oct. 05, 1998
TSC21020F
Functional Block Diagram
General Description
The TSC21020F is single-chip IEEE floating-point
processor optimized for digital signal processing
applications
1
. Its architecture is similar to that of Analog
Devices’ ADSP-2100 family of fixed-point DSP
processors.
Fabricated in a high-speed, low-power and radiation
tolerant CMOS process, the TSC21020F has a 50 ns
instruction cycle time. With a high-performance on-chip
instruction cache, the TSC21020F can execute every
instruction in a single cycle.
The TSC21020F features :
D
Independent Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and
shifter perform single-cycle instructions. The units
are architecturally arranged in parallel, maximizing
computational throughput. A single multifunction
instruction executes parallel ALU and multiplier
operations. These computation units support IEEE
32-bit single-precision floating-point, extended
precision 40-bit floating-point, and 32-bit fixed-point
data formats.
D
Data Register File
A general-purpose data register file is used for
transferring data between the computation units and
the data buses, and for storing intermediate results.
This 10-port (16-register) register file, combined with
the TSC21020F’s Harvard architecture, allows
2
Rev. E – Oct. 05, 1998
TSC21020F
unconstrained data flow between computation units
and off-chip memory.
D
Single-Cycle Fetch of Instruction and Two
Operands
The TSC21020F uses a modified Harvard architecture
in which data memory stores data and program
memory stores both instructions and data. Because of
its separate program and data memory buses and
on-chip instruction cache, the processor can
simultaneously fetch an operand from data memory,
an operand from program memory, and an instruction
from the cache, all in a single cycle.
D
Memory Interface
Addressing of external memory devices by the
TSC21020F is facilitated by on-chip decoding of
high-order address lines to generate memory bank
select signals. Separate control lines are also
generated for simplified addressing of page-mode
DRAM. The TSC21020F provides programmable
memory wait states, and external memory
acknowledge controls allow interfacing to peripheral
devices with variable access times.
D
Instruction Cache
The TSC21020F includes a high performance
instruction cache that enables three-bus operation for
fetching an instruction and two data values. The cache
is selective-only the instructions whose fetches
conflict with program memory data accesses are
cached. This allows full-speed execution of core,
looped operations such as digital filter
multiply-accumulates and FFT butterfly processing.
D
Hardware Circular Buffers
The TSC21020F provides hardware to implement
circular buffers in memory, which are common in
digital filters and Fourier transform implementations.
It handles address pointer wraparound, reducing
overhead (thereby increasing performance) and
simplifying implementation. Circular buffers can
start and end at any location.
D
Flexible Instruction Set
The TSC21020F’s 48-bit instruction word
accommodates a variety of parallel operations, for
concise programming. For example, the TSC21020F
can conditionally execute a multiply, an add, a
subtract and a branch in a single instruction.
1. It is fully compatible with Analog Devices ADSP-21020
3
Rev. E – Oct. 05, 1998
TSC21020F
Development System
The TSC21020F is supported with a complete set of
software and hardware development tools from Analog
Devices. The ADSP-21000 Family Development System
from Analog Devices includes development software, an
evaluation board and an in-circuit emulator.
D
Assembler
Creates relocatable, COFF (Common Object File
Format) object files from ADSP-21xxx assembly
source code. It accepts standard C preprocessor
directives for conditional assembly and macro
processing. The algebraic syntax of the ADSP-21xxx
assembly language facilitates coding and debugging
of DSP algorithms.
D
Linker/Librarian
The Linker processes separately assembled object
files and library files to create a single executable
program. It assigns memory locations to code and to
data in accordance with a user-defined architecture
file that describes the memory and I/O configuration
of the target system. The Librarian allows you to
group frequently used object files into a single library
file that can be linked with your main program.
D
Simulator
The Simulator performs interactive, instruction-level
simulation of ADSP-21xxx code within the hardware
configuration described by a system architecture file.
It flags illegal operations and supports full symbolic
disassembly. It provides an easy-to-use, window
oriented, graphical user interface that is identical to
the one used by the ADSP- 21020 EZ-ICE Emulator.
Commands are accessed from pull-down menus with
a mouse.
D
PROM Splitter
Formats an executable file into files that can be used
with an industry-standard PROM programmer.
D
C Compiler and Runtime Library
The C Compiler complies with ANSI specifications.
It takes advantage of the TSC21020F’s high-level
language architectural features and incorporates
optimizing algorithms to speed up the execution of
code. It includes an extensive runtime library with
over 100 standard and DSP-specific functions.
C Source Level Debugger
A full-featured C source level debugger that works
with the simulator or EZ-ICE emulator to allow
debugging of assembler source, C source, or mixed
assembler and C.
Numerical C Compiler
Supports ANSI Standard (X3J11.1) Numerical C as
defined by the Numeric C Extensions Group. The
compiler accepts C source input containing
Numerical C extensions for array selection, vector
math operations, complex data types, circular
pointers, and variably dimensioned arrays, and
outputs ADSP-21xxx assembly language source code.
ADSP- 21020 EZ-LAB
®
Evaluation Board
The EZ-LAB Evaluation Board is a general-purpose,
standalone TSC21020F system that includes 32K
words of program memory and 32K words of data
memory as well as analog I/O. A PC RS-232
download path enables the user to download and run
programs directly on the EZ-LAB. In addition, it may
be used in conjunction with the EZ-ICE Emulator to
provide a powerful software debug environment.
ADSP- 21020 EZ-ICE
®
Emulator
This in-circuit emulator provides the system designer
with a PC-based development environment that
allows nonintrusive access to the TSC21020F’s
internal registers through the processor’s 5-pin JTAG
Test Access Port. This use of on-chip emulation
circuitry enables reliable, full-speed performance in
any target. The emulator uses the same graphical user
interface as the ADSP- 21020 Simulator, allowing an
easy transition from software to hardware debug. (See
“Target System Requirements for Use of EZ-ICE
Emulator” on page 27.)
D
D
D
D
REZ-LAB
and EZ-ICE are registered trademarks of Analog Devices, Inc.
Additional Information
This data sheet provides a general overview of
TSC21020F functionality. For additional information on
the architecture and instruction set of the processor, refer
to the
ADSP-21020 User’s Manual.
For development
system and programming reference information, refer to
the
ADSP-21000 Family Development Software Manuals
and the
ADSP-21020 Programmer’s Quick Reference.
4
Rev. E – Oct. 05, 1998
TSC21020F
Architecture Overview
Figure 1 shows a block diagram of the TSC21020F. The
processor features:
D
Three Computation Units (ALU, Multiplier, and
Shifter) with a Shared Data Register File
D
Two Data Address Generators (DAG 1, DAG 2)
D
Program Sequencer with Instruction Cache
D
32-Bit Timer
D
Memory Buses and Interface
D
JTAG Test Access Port and On-Chip Emulation Support
multiplication as well as fixed-point multiply/add and
multiply/subtract operations. Integer products are 64 bits
wide, and the accumulator is 80 bits wide. The ALU
performs 45 standard arithmetic and logic operations,
supporting both fixed-point and floating-point formats.
The shifter performs 19 different operations on 32-bit
operands. These operations include logical and
arithmetic shifts, bit manipulation, field deposit, and
extract and derive exponent operations.
The computation units perform single-cycle operations ;
there is
no
computation pipeline. The three units are
connected in parallel rather than serially, via multiple-bus
connections with the 10-port data register file. The output
of any computation unit may be used as the input of any
unit on the next cycle. In a
multifunction
computation, the
ALU and multiplier perform independent, simultaneous
operations.
Computation Units
The TSC21020F contains three independent computation
units : an ALU, a multiplier with fixed-point
accumulator, and a shifter. In order to meet a wide variety
of processing needs, the computation units process data
in three formats : 32-bit fixed-point, 32-bit floating-point
and 40-bit floating-point. The floating-point operations
are single-precision IEEE-compatible (IEEE Standard
754/854). The 32-bit floating-point format is the standard
IEEE format, whereas the 40-bit IEEE extended-
precision format has eight additional LSBs of mantissa
for greater accuracy.
The multiplier performs floating-point and fixed-point
Data Register File
The TSC21020F’s general-purpose data register file is
used for transferring data between the computation units
and the data buses, and for storing intermediate results.
The register file has two sets (primary and alternate) of
sixteen 40-bit registers each, for fast context switching.
Figure 1. TSC21020F Block Diagram
5
Rev. E – Oct. 05, 1998
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
