multaneous sampling 16-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 76.8dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.07ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.4LSB
RMS
.
The digital outputs can be either full rate CMOS, Double
Data Rate CMOS, or Double Data Rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
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Two-Channel Simultaneously Sampling ADC
76.8dB SNR
90dB SFDR
Low Power: 370mW/308mW/200mW Total
185mW/154mW/100mW per Channel
Single 1.8V Supply
CMOS, DDR CMOS, or DDR LVDS Outputs
Selectable Input Ranges: 1V
P-P
to 2V
P-P
550MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
64-Pin (9mm
×
9mm) QFN Package
applicaTions
n
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Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
Typical applicaTion
1.8V
V
DD
1.8V
OV
DD
0
–10
CH 1
ANALOG
INPUT
–20
AMPLITUDE (dBFS)
S/H
16-BIT
ADC CORE
D1_15
•
•
•
D1_0
OUTPUT
DRIVERS
D2_15
•
•
•
D2_0
–30
–40
–50
–60
–70
–80
CMOS,
DDR CMOS
OR DDR LVDS
OUTPUTS
2-Tone FFT, f
IN
= 70MHz and 69MHz
CH 2
ANALOG
INPUT
S/H
16-BIT
ADC CORE
–90
–100
–110
–120
125MHz
CLOCK
GND
CLOCK
CONTROL
218543 TA01a
0
10
20
30
40
FREQUENCY (MHz)
50
60
218543
TA01b
OGND
218543f
1
LTC2185/LTC2184/LTC2183
absoluTe MaxiMuM raTings
(Notes 1, 2)
Supply Voltages (V
DD
, OV
DD
) ....................... –0.3V to 2V
Analog Input Voltage (A
IN+
, A
IN–
,
PAR/SER, SENSE) (Note 3) .......... –0.3V to (V
DD
+ 0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTC2185C, 2184C, 2183C ........................ 0°C to 70°C
LTC2185I, 2184I, 2183I ....................... –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
pin conFiguraTions
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
64 V
DD
63 SENSE
62 V
REF
61 SDO
60 OF1
59 OF2
58 D1_15
57 D1_14
56 D1_13
55 D1_12
54 D1_11
53 D1_10
52 D1_9
51 D1_8
50 D1_7
49 D1_6
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
64 V
DD
63 SENSE
62 V
REF
61 SDO
60 OF2_1
59 DNC
58 D1_14_15
57 DNC
56 D1_12_13
55 DNC
54 D1_10_11
53 DNC
52 D1_8_9
51 DNC
50 D1_6_7
49 DNC
48 D1_5
47 D1_4
46 D1_3
45 D1_2
44 D1_1
43 D1_0
42 OV
DD
41 OGND
40 CLKOUT
+
39 CLKOUT
–
38 D2_15
37 D2_14
36 D2_13
35 D2_12
34 D2_11
33 D2_10
V
DD
1
V
CM1
2
GND 3
A
IN1+
4
A
IN1–
5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
A
IN2+
12
A
IN2–
13
GND 14
V
CM2
15
V
DD
16
65
GND
48 D1_4_5
47 DNC
46 D1_2_3
45 DNC
44 D1_0_1
43 DNC
42 OV
DD
41 OGND
40 CLKOUT
+
39 CLKOUT
–
38 D2_14_15
37 DNC
36 D2_12_13
35 DNC
34 D2_10_11
33 DNC
UP PACKAGE
64-LEAD (9mm
×
9mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
V
DD
17
ENC
+
18
ENC
–
19
CS
20
SCK 21
SDI 22
DNC 23
D2_0_1 24
DNC 25
D2_2_3 26
DNC 27
D2_4_5 28
DNC 29
D2_6_7 30
DNC 31
D2_8_9 32
V
DD
1
V
CM1
2
GND 3
A
IN1+
4
A
IN1–
5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
A
IN2+
12
A
IN2–
13
GND 14
V
CM2
15
V
DD
16
65
GND
UP PACKAGE
64-LEAD (9mm
×
9mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
V
DD
17
ENC
+
18
ENC
–
19
CS
20
SCK 21
SDI 22
D2_0 23
D2_1 24
D2_2 25
D2_3 26
D2_4 27
D2_5 28
D2_6 29
D2_7 30
D2_8 31
D2_9 32
218543f
2
LTC2185/LTC2184/LTC2183
pin conFiguraTions
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
64 V
DD
63 SENSE
62 V
REF
61 SDO
60 OF2_1
+
59 OF2_1
–
58 D1_14_15
+
57 D1_14_15
–
56 D1_12_13
+
55 D1_12_13
–
54 D1_10_11
+
53 D1_10_11
–
52 D1_8_9
+
51 D1_8_9
–
50 D1_6_7
+
49 D1_6_7
–
V
DD
1
V
CM1
2
GND 3
A
IN1+
4
A
IN1–
5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
A
IN2+
12
A
IN2–
13
GND 14
V
CM2
15
V
DD
16
65
GND
48 D1_4_5
+
47 D1_4_5
–
46 D1_2_3
+
45 D1_2_3
–
44 D1_0_1
+
43 D1_0_1
–
42 OV
DD
41 OGND
40 CLKOUT
+
39 CLKOUT
–
38 D2_14_15
+
37 D2_14_15
–
36 D2_12_13
+
35 D2_12_13
–
34 D2_10_11
+
33 D2_10_11
–
UP PACKAGE
64-LEAD (9mm
×
9mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC2185CUP#PBF
LTC2185IUP#PBF
LTC2184CUP#PBF
LTC2184IUP#PBF
LTC2183CUP#PBF
LTC2183IUP#PBF
TAPE AND REEL
LTC2185CUP#TRPBF
LTC2185IUP#TRPBF
LTC2184CUP#TRPBF
LTC2184IUP#TRPBF
LTC2183CUP#TRPBF
LTC2183IUP#TRPBF
PART MARKING*
LTC2185UP
LTC2185UP
LTC2184UP
LTC2184UP
LTC2183UP
LTC2183UP
PACKAGE DESCRIPTION
64-Lead (9mm
×
9mm) Plastic QFN
64-Lead (9mm
×
9mm) Plastic QFN
64-Lead (9mm
×
9mm) Plastic QFN
64-Lead (9mm
×
9mm) Plastic QFN
64-Lead (9mm
×
9mm) Plastic QFN
64-Lead (9mm
×
9mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
V
DD
17
ENC
+
18
ENC
–
19
CS
20
SCK 21
SDI 22
D2_0_1
–
23
D2_0_1
+
24
D2_2_3
–
25
D2_2_3
+
26
D2_4_5
–
27
D2_4_5
+
28
D2_6_7
–
29
D2_6_7
+
30
D2_8_9
–
31
D2_8_9
+
32
218543f
3
LTC2185/LTC2184/LTC2183
converTer characTerisTics
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
Internal Reference
External Reference
Differential Analog Input
(Note 7)
Internal Reference
External Reference
CONDITIONS
l
LTC2185
MIN
16
–7.5
–0.9
–7
–2.3
±2
±0.5
±1.5
±1.5
–0.9
±10
±30
±10
±0.3
±1.5
3.4
7.5
0.9
7
0.3
TYP
MAX
MIN
16
–7.5
–0.9
–7
–2.1
LTC2184
TYP
±2
±0.5
±1.5
±1.5
–0.8
±10
±30
±10
±0.3
±1.5
3.5
MAX
7.5
0.9
7
0.4
MIN
16
–7.5
–0.9
–7
–1.8
LTC2183
TYP
±2
±0.5
±1.5
±1.5
–0.5
±10
±30
±10
±0.3
±1.5
3.2
MAX
7.5
0.9
7
0.8
UNITS
Bits
LSB
LSB
mV
%FS
%FS
µV/°C
ppm/°C
ppm/°C
%FS
mV
LSB
RMS
Differential Analog Input (Note 6)
l
l
l
l
analog inpuT
SYMBOL PARAMETER
V
IN
V
IN(CM)
V
SENSE
I
INCM
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
0 < A
IN+
, A
IN–
< V
DD
0 < PAR/SER < V
DD
0.625 < SENSE < 1.3V
Single-Ended Encode
Differential Encode
Figure 6 Test Circuit
l
l
l
l
l
l
MIN
0.7
0.625
TYP
1 to 2
V
CM
1.250
200
170
130
MAX
1.25
1.300
UNITS
V
P-P
V
V
µA
µA
µA
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
Analog Input Common Mode Current
External Voltage Reference Applied to SENSE External Reference Mode
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
–1.5
–3
–3
0
0.07
0.09
80
550
1.5
3
3
µA
µA
µA
ns
ps
RMS
ps
RMS
dB
MHz
218543f
4
LTC2185/LTC2184/LTC2183
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
LTC2185
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
CONDITIONS
5MHz Input
70MHz Input
140MHz Input
l
DynaMic accuracy
LTC2184
MAX
MIN
74.8
TYP
76.7
76.5
76
90
89
84
90
89
84
95
95
95
76.5
76.1
75
–110
MAX
MIN
75.1
LTC2183
TYP
77.1
76.9
76.4
90
89
84
90
89
84
95
95
95
76.9
76.5
75.3
–110
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
MIN
74.8
TYP
76.8
76.6
76.1
90
89
84
90
89
84
95
95
95
76.6
76.2
75.1
–110
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd Harmonic
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
3rd Harmonic
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
l
79
81
81
l
82
81
82
l
89
89
89
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
Crosstalk
5MHz Input
70MHz Input
140MHz Input
10MHz Input
l
73.3
73.9
74.4
inTernal reFerence characTerisTics
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400µA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600µA < I
OUT
< 1mA
I
OUT
= 0
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
FPGA/CPLD
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