SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50307-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (×8/×16) FLASH MEMORY &
4M (×8/×16) STATIC RAM
MB84VD2118XEM
-70
/MB84VD2119XEM
-70
s
FEATURES
• Power Supply Voltage of 2.7 V to 3.3 V
•
High Performance
70 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
•
Operating Temperature
–40
°
C to +85
°
C
• Package 56-ball FBGA
(Continued)
s
PRODUCT LINE-UP
Part No.
Supply Voltage(V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
MB84VD2118XEM/MB84VD2119XEM
V
CC
f*= 3.0 V
70
70
30
+0.3 V
–0.3 V
V
CC
s*= 3.0 V
+0.3V
–0.3 V
70
70
35
*: Both V
CC
f and V
CC
s must be in recommended operation range when either part is being accessed.
s
PACKAGE
56-ball plastic FBGA
(BGA-56P-M02)
MB84VD2118XEM/2119XEM
-70
(Continued)
•
FLASH MEMORY
•
Simultaneous Read/Write Operations (Dual Bank)
Miltiple devices available with different bank sizes (Please refer to ORDERING INFORMATION)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
•
Sector Erase Architecture
Eight 4 K words and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
•
Boot Code Sector Architecture
MB84VD2118XEM: Top sector
MB84VD2119XEM: Bottom sector
•
Embedded Erase
TM
* Algorithms
Automatically pre-programs and erases the chip or any sector
•
Embedded Program
TM
* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
•
Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
•
Low V
CC
Write Inhibit
≤
2.5 V
•
HiddenROM Region
64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•
WP/ACC Input Pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2118XEM:SA37,SA38 MB84VD2119XEM:SA0,SA1)
At V
IH
, allows removal of boot sector protection
At V
ACC
, program time will reduse by 40%.
•
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL16XTE/BE” Datasheet in Detailed Function
•
SRAM
•
Power Dissipation
Operating : 40 mA Max
Standby : 10
µ
A Max
• Power Down Features using CE1s and CE2s
• Data Retention Supply Voltage: 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte Data Control: LB (DQ
7
to DQ
0
), UB (DQ
15
to DQ
8
)
* : Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
2
MB84VD2118XEM/2119XEM
-70
s
PIN DESCRIPTION
Pin Name
A
17
to A
0
A
19
, A
18
, A
-1
SA
DQ
15
to DQ
0
CEf
CE1s
CE2s
OE
WE
RY/BY
UB
LB
CIOf
Function
Address Inputs (Common)
Address Input (Flash)
Address Input (SRAM)
Data Inputs / Outputs (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash) Open Drain
Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
I/O Configuration (Flash)
CIOf
=
V
CC
f is Word mode (
×
16),
CIOf
=
V
SS
is Byte mode (
×
8)
I/O Configuration (SRAM)
CIOs
=
V
CC
s is Word mode (
×
16),
CIOs
=
V
SS
is Byte mode (
×
8)
Hardware Reset Pin / Sector Protection
Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (SRAM)
I/O
I
I
I
I/O
I
I
I
I
I
O
I
I
I
CIOs
I
RESET
WP/ACC
N.C.
V
SS
V
CC
f
V
CC
s
I
I
—
Power
Power
Power
4
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