FUJITSU SEMICONDUCTOR
DATA SHEET
AE3E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (× 8/×16) FLASH MEMORY &
4M (× 8/×16) STATIC RAM
MB84VD2118XA
-85
/MB84VD2119XA
-85
s
FEATURES
• Power supply voltage of 2.7 to 3.6 V
• High performance
85 ns maximum access time
• Operating Temperature
–25 to +85°C
• Package 69-ball BGA , 56-pin TSOP
— FLASH MEMORY
• Simultaneous Read/Write operations (dual bank)
Miltiple devices available with different bank sizes (Refer to Table 1)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 write/erase cycles
• Sector erase architecture
Eight 4 K words and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VD2118XA: Top sector
MB84VD2119XA: Bottom sector
• Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low V
CC
write inhibit
≤
2.5 V
• Hidden ROM (Hi-ROM) region
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
(Continued)
MB84VD2118XA
-85
/MB84VD2119XA
-85
(Continued)
• WP/ACC input pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2118XA:SA37,SA38 MB84VD2119XA:SA0,SA1)
At V
IH
, allows removal of boot sector protection
At V
ACC
, program time will reduse by 40%.
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL16XTD/BD” data sheet in detailed function
— SRAM
• Power dissipation
Operating : 40 mA max.
Standby : 7
µA
max.
• Power down features using CE1s and CE2s
• Data retention supply voltage: 1.5 V to 3.6 V
• CE1s and CE2s Chip Select
• Byte data control: LBs(DQ
0
-DQ
7
), UBs(DQ
8
-DQ
15
)
s
BLOCK DIAGRAM
V
CC
f
A
0
to A
19
A
0
to A
19
A
–1
WP/ACC
RESET
CEf
CIOf
V
SS
RY/BY
16 M bit
Flash Memory
DQ
0
to DQ
15
/A
–
1
DQ
0
to DQ
15
/A
–
1
V
CC
s
A
0
to A
17
DQ
0
to DQ
15
V
SS
SA
LBs
UBs
WE
OE
CE1s
CE2s
CIOs
4 M bit
Static RAM
2
MB84VD2118XA
-85
/MB84VD2119XA
-85
Table 1 Pin Configuration
Pin
A
0
to A
17
A
–1
, A
18
to A
19
SA
DQ
0
to DQ
15
CEf
CE1s
CE2s
OE
WE
RY/BY
UBs
LBs
CIOf
CIOs
RESET
WP/ACC
N.C.
V
SS
V
CC
f
V
CC
s
Function
Address Inputs (Common)
Address Input (Flash)
Address Input (SRAM)
Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
I/O Configulation (Flash)
CIOf = V
IH
is Word mode (×16), CIOf = V
IL
is Byte mode (×8)
I/O Configulation (SRAM)
CIOs = V
IH
is Word mode (×16), CIOs = V
IL
is Byte mode (×8)
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect / Accelaration (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (SRAM)
Input/
Output
I
I
I
I/O
I
I
I
I
I
O
I
I
I
I
I
I
—
Power
Power
Power
s
PRODUCT LINE UP
Flash Memory
Ordering Part No.
V
CC
= 3.0 V
+0.6 V
–0.3 V
SRAM
MB84VD2118XA-85/MB84VD2119XA-85
85
85
35
85
85
45
5
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
PCB设计
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