210Msps/170Msps 14-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 70dB SNR and 90dB
spurious free dynamic range (SFDR). The latency is only
five clock cycles.
DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.82LSB
RMS
.
The digital outputs are Double-Data Rate (DDR) LVDS.
The ENC
+
and ENC
–
inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
70dB SNR
90dB SFDR
Low Power: 338mW/316mW/290mW Total
Single 1.8V Supply
DDR LVDS Outputs
Easy-to-Drive 1.5V
P-P
Input Range
1.25GHz Full Power Bandwidth S/H
Optional Clock Duty Cycle Stabilizer
Low Power Sleep and Nap Modes
Serial SPI Port for Configuration
Pin Compatible with 12-Bit Versions
40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
n
n
n
n
n
n
Communications
Cellular Basestations
Software Defined Radios
Medical Imaging
High Definition Video
Testing and Measurement Instruments
TYPICAL APPLICATION
V
DD
OV
DD
D12_13
•
•
•
D0_1
32K Point FFT,
f
IN
= 15MHz, –1dBFS, 250Msps
0
–20
AMPLITUDE (dBFS)
ANALOG
INPUT
S/H
14-BIT
PIPELINED
ADC
CORRECTION
LOGIC
OUTPUT
DRIVERS
DDR
LVDS
–40
–60
–80
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
21521014 TA01a
OGND
–100
–120
0
20
40
60
80
100
FREQUENCY (MHz)
120
21521014 TA01b
21521014p
1
LTC2152-14/
LTC2151-14/LTC2150-14
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
TOP VIEW
PAR/SER
D12_13
+
D12_13
–
D10_11
+
D2_3
+
D10_11
–
30 OV
DD
29 D8_9
+
28 D8_9
–
27 CLKOUT
+
GND
41
26 CLKOUT
–
25 D6_7
+
24 D6_7
–
23 D4_5
+
22 D4_5
–
21 OGND
11 12 13 14 15 16 17 18 19 20
GND
D0_1
–
D0_1
+
D2_3
–
OV
DD
ENC
+
–
–
+
Supply Voltage
V
DD
, OV
DD
................................................ –0.3V to 2V
Analog Input Voltage
A
INA/B+
, A
INA/B –
, PAR/SER,
SENSE (Note 3)........................ –0.3V to (V
DD
+ 0.2V)
Digital Input Voltage
ENC
+
, ENC
–
(Note 3) ................ –0.3V to (V
DD
+ 3.9V)
CS,
SDI, SCK (Note 4).............. –0.3V to (V
DD
+ 0.3V)
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTC2152C, LTC2151C, LTC2150C ............. 0°C to 70°C
LTC2152I, LTC2151I, LTC2150I ............–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
40 39 38 37 36 35 34 33 32 31
V
DD
1
V
DD
2
GND 3
A
IN+
4
A
IN–
5
GND 6
SENSE 7
VREF 8
VCM 9
GND 10
ENC
OF
UJ PACKAGE
40-LEAD (6mm
×
6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 33°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2152CUP-14#PBF
LTC2152IUP-14#PBF
LTC2151CUP-14#PBF
LTC2151IUP-14#PBF
LTC2150CUP-14#PBF
LTC2150IUP-14#PBF
TAPE AND REEL
LTC2152CUP-14#TRPBF
LTC2152IUP-14#TRPBF
LTC2151CUP-14#TRPBF
LTC2151IUP-14#TRPBF
LTC2150CUP-14#TRPBF
LTC2150IUP-14#TRPBF
PART MARKING*
LTC2152-14
LTC2152-14
LTC2151-14
LTC2151-14
LTC2150-14
LTC2150-14
PACKAGE DESCRIPTION
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
OF
GND
SDO
SCK
SDI
CS
21521014p
2
LTC2152-14/
LTC2151-14/LTC2150-14
CONVERTER CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
l
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Transition Noise
MIN
14
–3.7
–1
–15
LTC2152-14
TYP MAX
±0.85
±0.5
±5
±1
±20
±30
±10
1.85
3.7
1
15
MIN
14
–3.8
–1
–15
LTC2151-14
TYP MAX
±1
±0.5
±5
±1
±20
±30
±10
1.8
3.8
1
15
LTC2150-14
MIN
TYP MAX
14
–3.8
–1
–15
±1
±0.5
±3
±1
±20
±30
±10
1.8
3.8
1
15
UNITS
Bits
LSB
LSB
mV
%FS
µV/°C
ppm/°C
ppm/°C
LSB
RMS
Differential Analog Input (Note 6)
l
Differential Analog Input
(Note 7)
External Reference
Internal Reference
External Reference
External Reference
l
l
l
ANALOG INPUT
SYMBOL PARAMETER
V
IN
V
IN(CM)
V
SENSE
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
External Reference Mode
0 < A
IN+
, A
IN–
< V
DD
1.2V < SENSE < 1.3V
0 < PAR/SER < V
DD
l
l
l
l
l
l
MIN
V
CM
– 20mV
1.200
–1
–1
–1
TYP
1.5
V
CM
1.250
MAX
V
CM
+ 20mV
1.300
1
1
1
UNITS
V
P-P
V
V
µA
µA
µA
ns
ps
RMS
dB
MHz
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
External Reference Mode
Analog Input Leakage Current
SENSE Input Leakage Current
PAR/SER Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
1
0.15
75
1250
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
CONDITIONS
5MHz Input
70MHz Input
140MHz Input
MIN
LTC2152-14
TYP MAX
70
69.7
69
90
85
80
95
95
85
69.9
69.4
68.8
MIN
LTC2151-14
TYP MAX
70
69.7
69
90
85
80
95
95
85
69.9
69.4
68.8
LTC2150-14
MIN
TYP MAX
70
69.7
69
90
85
80
98
95
85
69.9
69.4
68.8
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
DYNAMIC ACCURACY
l
TBD
TBD
TBD
TBD
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
l
TBD
TBD
l
TBD
TBD
TBD
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
l
TBD
TBD
TBD
21521014p
3
LTC2152-14/
LTC2151-14/LTC2150-14
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400µA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–1mA < I
OUT
< 1mA
I
OUT
= 0
1.225
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
MIN
0.444 •
V
DD
– 15mV
TYP
0.444 •
V
DD
±37
4
1.250
±30
7
0.6
1.275
MAX
0.444 •
V
DD
+ 15mV
UNITS
V
ppm/°C
Ω
V
ppm/°C
Ω
mV/V
POWER REQUIREMENTS
SYMBOL PARAMETER
V
DD
OV
DD
I
VDD
I
OVDD
P
DISS
P
SLEEP
P
NAP
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
Power Dissipation
Nap Mode Power
Sleep Mode Power
CONDITIONS
(Note 9)
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
MIN
l
l
l
LTC2152-14
TYP MAX
1.8
1.8
160
28
47
338
372
113.5
<2
1.9
1.9
MIN
1.7
1.7
LTC2151-14
TYP MAX
1.8
1.8
149
27
45
316
249
106.2
<2
1.9
1.9
LTC2150-14
MIN
TYP MAX
1.7
1.7
1.8
1.8
135
26
44
290
322
97.2
<2
1.9
1.9
UNITS
V
V
mA
mA
mA
mW
mW
mW
mW
1.7
1.7
LVDS Mode (Note 9)
1.75mA LVDS Mode
3.5mA LVDS Mode
1.75mA LVDS Mode
3.5mA LVDS Mode
Clocked at f
S(MAX)
Clocked at f
S(MAX)
l
l
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER
ENCODE INPUTS (ENC
+
, ENC
–
)
V
ID
V
ICM
V
IN
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
R
OL
I
OH
C
OUT
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
(Note 8)
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
l
l
l
MIN
0.2
1.1
0.2
TYP
1
1.2
MAX
1.9
1.5
1.9
UNITS
V
V
V
V
kΩ
pF
V
Internally Set
Externally Set (Note 8)
ENC
+
, ENC
–
to GND
(See Figure 2)
(Note 8)
V
DD
= 1.8V
V
DD
= 1.8V
V
IN
= 0V to 1.8V
(Note 8)
V
DD
= 1.8V, SDO = 0V
SDO = 0V to 3.6V
(Note 8)
10
2
l
l
l
DIGITAL INPUTS (CS, SDI, SCK)
1.3
0.6
–10
3
200
l
V
µA
pF
Ω
10
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
–10
4
10
µA
pF
21521014p
4
LTC2152-14/
LTC2151-14/LTC2150-14
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER
DIGITAL DATA OUTPUTS
V
OD
V
OS
R
TERM
Differential Output Voltage
Common Mode Output Voltage
On-Chip Termination Resistance
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OV
DD
= 1.8V
l
l
l
l
MIN
247
125
1.125
1.125
TYP
350
175
1.250
1.250
100
MAX
454
250
1.375
1.375
UNITS
mV
mV
V
V
Ω
TIMING CHARACTERISTICS
SYMBOL
f
S
t
L
t
H
PARAMETER
Sampling Frequency
ENC Low Time (Note 8)
ENC High Time (Note 8)
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
LTC2152-14
MIN
TYP MAX
10
250
1.9
2
50
1.9
2
50
1.9
2
50
1.9
2
50
LTC2151-14
MIN
TYP MAX
10
210
2.26 2.38
50
1.5
2.38
50
2.26 2.38
50
1.5
2.38
50
LTC2150-14
MIN
TYP MAX
10
170
2.79 2.94
50
1.5
2.94
50
2.79 2.94
50
1.5
2.94
50
UNITS
MHz
ns
ns
ns
ns
l
l
l
l
l
DIGITAL DATA OUTPUTS
LTC215X-14
SYMBOL
t
D
t
C
t
SKEW
PARAMETER
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
SPI Port Timing (Note 8)
t
SCK
t
S
t
H
t
DS
t
DH
t
DO
SCK Period
CS
to SCK Set-Up Time
SCK to
CS
Hold Time
SDI Set-Up Time
SDI Hold Time
SCK Falling to SDO Valid
Readback Mode R
PULLUP
= 2k, C
SDO
= 20pF
Write Mode, C
SDO
= 20pF
Readback Mode R
PULLUP
= 2k, C
SDO
= 20pF
l
l
l
l
l
CONDITIONS
C
L
= 5pF
C
L
= 5pF
t
D
– t
C
MIN
l
l
l
TYP
2
1.6
0.4
MAX
2.3
2
0.55
5
UNITS
ns
ns
ns
Cycles
ns
ns
ns
ns
ns
ns
1.7
1.3
0.3
5
40
250
5
5
5
5
125
ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3:
When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
DD
without latchup.
Note 4:
When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V
DD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5:
V
DD
= OV
DD
= 1.8V, f
SAMPLE
= 250MHz (LTC2152),
210MHz (LTC2151), or 170MHz (LTC2150), LVDS outputs, differential
ENC
+
/ENC
–
= 2V
P-P
sine wave, input range = 1.5V
P-P
with differential
drive, unless otherwise noted.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7:
Offset error is the offset voltage measured from –0.5LSB when the
output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111
EtherCAT（Ethernet for Control Automation Technology）是一种基于以太网的开发构架的实时工业现场总线通讯协议，EtherCAT是最快的工业以太网技术之一，同时它提供纳秒级精确同步。相对于设置了相同循环时间的其他总线系统，EtherCAT系统结构通常能减少25%-30%的CPU负载，EtherCAT的出现为系统的实时性能和拓扑的灵活性树立了新的标准。...[详细]
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