32K x 32 SRAM MODULE
PUMA 2S1000 - 020/025/35/45
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.3 : November 1998
Description
The PUMA 2S1000 is a 1Mbit high speed static RAM
organised as 32K x 32 in a 66 pin ceramic PGA
package. Access times of 20ns, 25ns, 35ns or 45ns
are available. The device has a user configurable
output width by 8 ,16 or 32 bits, and features a low
power standby mode with 3.0V battery back-up
capability. The package includes on board
decoupling capacitors and is suitable for thermal
ladder operations.
It may be screened in accordance with
MIL-STD-883.
1,048,576 bit CMOS High Speed Static RAM
Features
• Very Fast Access times of 20/25/35/45 ns.
• User Configurable as 8 / 16 / 32 bit wide output.
• Operating Power
1.6 W (max) 8 bit
• Low Power Standby 44 mW (max) - L Version
• Upgradeable Package.
• Package Suitable for Thermal Ladder Applications.
• On board decoupling capacitors.
• Low voltage data retention.
• May be screened in accordance with MIL-STD-883.
Block Diagram
Pin Definition
1
A0~A14
OE
WE4
WE3
WE2
WE1
12
WE2
13
CS2
14
GND
15
D11
16
A10
17
A11
18
A12
19
VCC
20
CS1
21
NC
22
D3
23
D15
24
D14
25
D13
26
D12
27
OE
28
NC
29
WE1
30
D7
31
D6
32
D5
33
D4
34
D24
35
D25
36
D26
37
45
VCC
46
CS4
47
WE4
48
D27
49
A3
50
A4
51
A5
52
WE3
53
CS3
54
GND
55
D19
56
D31
57
D30
58
D29
59
D28
60
A0
61
A1
62
A2
63
D23
64
D22
65
D21
66
D20
D8
2
D9
3
D10
4
A13
5
A14
6
NC
7
NC
8
NC
9
D0
10
D1
11
D2
32Kx8
SRAM
CS1
CS2
CS3
CS4
D0~D7
D8~D15
D16~D23
D24~D31
32Kx8
SRAM
32Kx8
SRAM
32Kx8
SRAM
VIEW
FROM
ABOVE
A6
38
A7
39
NC
40
A8
41
A9
42
D16
43
D17
44
D18
Pin Functions
A0~A14
CS1~4
WE1~4
V
CC
Address Inputs
Chip Select
Write Enable
Power (+5V)
D0~D31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground
ISSUE 4.3 : November 1998
PUMA 2S1000 - 25/35/45
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Voltage on any pin relative to V
SS (2)
Power Dissipation
Storage Temperature
V
T
P
T
T
STG
-0.5V to +7.0
4
-65 to +150
V
W
o
C
Notes :
(1)Stresses above those listed may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
(2) Pulse width:- 3.0V for less than 10ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
T
AM
min
4.5
2.2
-0.5
0
-40
-55
typ
(1)
5.0
-
-
-
-
-
max
5.5
V
CC
+0.5
0.8
70
85
125
Unit
V
V
V
o
o
C
C
C
(I suffixI)
(M,
MB
suffix)
o
DC Electrical Characteristics
(V
CC
=5V±10%,T
A
=-55
°
C to +125°C)
Parameter
I/P Leakage Current
Output Leakage Current
Average Supply Current
Symbol
I
LI1
8 bit
32 bit
16 bit
8 bit
I
LO
I
CC32
I
CC16
I
CC8
I
SB
I
SB2
V
OL
V
OH
Test Condition
V
IN
=0V to V
CC
CS
(2)
=V
IL
, Min. cycle, I
I/O
=0mA, 100% Duty.
As above
As above
CS
(2)
=V
IH
, Min Cycle.
CS
(2)
≥V
CC
-0.2V, 0.2V≥V
IN
≥V
CC
-0.2V
I
OL
=8.0mA
I
OH
=-4.0mA
min
-8
-
-
-
-
-
-
2.4
typ
(1)
-
-
-
-
-
-
-
-
-
max Unit
8
8
660
410
285
160
8
0.4
-
µA
µA
mA
mA
mA
mA
mA
V
V
CS
(2)
=V
IH
or OE=V
IH
,V
I/O
=0V to V
CC
,WE
(2)
=V
IL
-8
Standby Supply Current
Output Voltage Low
Output Voltage High
Notes:
TTL
-L Version
CS and WE above are accessed through CS1~4 and WE1~4 respectively. These inputs must be operated
simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
Capacitance
(V
CC
=5V±10%,T
A
=25
°
C)
Parameter
Input Capacitance
I/O Capacitance:
Symbol
C
IN
C
I/O
Test Condition
V
IN
=0V
V
I/O
=0V
typ
-
-
max
38
18
Unit
pF
pF
Note:This parameter is calculated and not measured.
2
PUMA 2S1000 - 25/35/45
ISSUE 4.3 : November 1998
Operating Modes
The Table below shows the logic inputs required to control the operating modes of each of the SRAMs on the
PUMA 2S1000.
Mode
Not Selected
OutputDisable
Read
Write
1 = V
IH
,
CS
1
0
0
0
OE
X
1
0
X
WE
X
1
1
0
V
CC
Current
I
SB
,I
SB1
,I
SB2
I
CC
I
CC
I
CC
X = Don't Care
I/O Pin Reference Cycle
High Z
High Z
D
OUT
D
IN
Read Cycle
Write Cycle
Power Down
0 = V
IL
,
Note: CS is accessed through CS1~4, and WE is accessed through WE1~4. For correct operation, CS1~4 must
operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation. WE1~4
must also be operated in the same manner.
Low V
cc
Data Retention Characteristics - L Version Only
(V
CC
= 5.0V±10%, T
A
=-55°C to +125°C)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Symbol
V
DR
I
CCDR1
-L Version I
CCDR2
t
CDR
t
R
Test Condition
CS≥V
CC
-0.2V, V
IN
≥0V
As above
See Retention Waveform
See Retention Waveform
min
2.0
-
0
t
RC
typ
-
-
-
-
-
max
5.5
8
1.2
-
-
Unit
V
mA
mA
ns
ns
V
CC
=2.0V, CS≥V
CC
-0.2V, V
IN
≥0V
-
Note: CS above is accessed through CS1~4.
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 3ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
cc
=5V±10%
Output Load
I/O Pin
166
Ω
1.76V
30pF
3
ISSUE 4.3 : November 1998
PUMA 2S1000 - 25/35/45
AC OPERATING CONDITIONS
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
OHZ
20
min max
20
-
-
-
3
3
0
0
0
-
20
20
9
-
-
-
8
8
25
min max
25
-
-
-
35
min max
35
-
-
-
5
6
0
0
0
-
35
35
15
-
-
-
15
15
45
min max
45
-
-
-
5
6
0
0
0
-
45
45
20
-
-
-
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
25
25
12
-
-
-
12
12
5
6
0
0
0
Chip Deselection to Output in High Z
(3)
t
CHZ
Output Disable to Output in High Z
(3)
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
20
min max
20
13
13
0
13
0
0
10
0
0
-
-
-
-
-
-
8
-
-
-
25
min max
25
20
20
0
15
0
0
20
0
5
-
-
-
-
-
-
15
-
-
-
35
min max
35
30
30
0
20
0
0
20
0
5
-
-
-
-
-
-
18
-
-
-
45
min
45
40
40
0
25
0
0
20
0
5
max
-
-
-
-
-
-
20
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Under Development
4
PUMA 2S1000 - 25/35/45
ISSUE 4.3 : November 1998
Read Cycle 1 Timing Waveform
(1)
t
Address
RC
t
AA
OE
t
OE
t
OLZ
CS1~4
t
OH
t
CLZ
t
ACS
t
CHZ(3)
t
OHZ(3)
Dout
High-Z
Data Valid
Read Cycle 2 Timing Waveform
(1) (2) (4)
t
RC
Address
t
AA
t
OH
t
OH
Dout
Data Valid
Notes: (1) WE1~4 is High for Read Cycle.
(2) Device is continuously selected, CS1~4=V
IL
.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
(4) OE=V
IL
.
5
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