128K x 32 EEPROM Module
PUMA 2/67/77E4001/A - 12/15/20
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.2 : November 1998
Description
Available in PGA (Puma 2), JLCC (Puma 67) and
Gullwing (Puma 77) footprints, the Puma **E4001 is
a 4 Mbit EEPROM module user configurable as
128K x 32, 256K x 16 or 512K x 8. Available with
access times of 120, 150 and 200ns, the device
features hardware and software data protection,
10,000 cycle Write/Erase capability and 10 year
data retention time.
An option of independant (A version) or single WE
control is available.
Parts may be screened in accordance with MIL-
STD-883
Features
• 4 Megabit EEPROM module.
• Access Times of 120/150/200 ns.
• Output Configurable as 32/ 16/ 8 bit wide.
• Upgradeable footprint
• Operating Power 1600/ 830/ 445 mW (Max).
Low Power Standby
2.2 mW (Max).
• Byte and Page Write (128 Bytes) in 5ms typical with
DATA Polling and Toggle bit indication of end of
Write.
• Hardware and Software Data Protection.
• Puma 2 - 66 pin Ceramic PGA.
• Puma 67 - 68 Lead Ceramic JLCC.
• Puma 77 - 68 Lead Ceramic Gullwing.
• May be screened in accordance with MIL-STD-883.
• 100,000 W/E cycle endurance option
Block Diagram
PUMA 2E4001, 67E4001A and 77E4001A
Block Diagram
PUMA 67E4001 and 77E4001
A0~A16
OE
WE4
WE3
WE2
WE1
A0~A16
OE
WE
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
128K x 8
EEPROM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
Pin Functions
A0~A16
CS1~4
OE
GND
Address Input
Chip Select
Output Enable
Ground
D0~D31
WE1~4
Vcc
Data Inputs/Outputs
Write Enables
Power (+5V)
ISSUE 4.2 : November 1998
PUMA 2/67/77E4001/A - 12/15/20
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Operating Temperature
Storage Temperature
Input voltages (including N.C. pins) with Respect to GND
Output voltages with respect to GND
T
OPR
T
STG
V
IN
V
OUT
-55 to +125
-65 to +150
-0.6 to +6.25
-0.6 to V
CC
+0.6
C
°
C
V
V
°
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operating Conditions
min
DC Power Supply Voltage
Input Low Voltage
Input High Voltage
Operating Temp Range
V
CC
V
IL
V
IH
T
A
T
AI
T
AM
4.5
-1.0
2.0
0
-40
-55
typ
5.0
-
-
-
-
-
max
5.5
0.8
V
CC
+1
70
85
125
V
V
V
°
C
°
C (I Suffix)
°
C (M,
MB
Suffix)
DC Electrical Characteristics
(T
A
=-55°C to +125°C,V
CC
=5V ± 10%)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Symbol
I
LI1
32 bit I
LO
32 bit I
CC32
16 bit I
CC16
8 bit I
CC8
Test Condition
min
-
-
-
-
-
-
-
-
2.4
max
40
40
320
166
89
12
1.2
0.45
-
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
V
IN
= GND to V
CC
+1
V
I/O
= GND to V
CC
, CS
(1)
=V
IH
CS
(1)
=OE=V
IL
, WE=V
IH
, I
OUT
=0mA, ƒ=5MHz
(2)
As above
As above
CS
(1)
= 2.0V to V
CC
+1V
CS
(1)
= V
CC
-0.3V to V
CC
+1V
I
OL
= 2.1mA.
I
OH
= -400µA.
Standby Supply Current TTL levels I
SB1
CMOS levels I
SB2
Output Low Voltage
Output High Voltage
V
OL
V
OH
Notes (1) CS above are accessed through CS1~4. These inputs must be operated simultaneously for 32 bit operation, in
pairs in 16 bit mode and singly for 8 bit mode.
(2) Also for WE1~4 on the PUMA 2E4001, 67E4001A, 77E4001A versions. Additionally, WE1~4 are accessed as in
note (1) above.
Capacitance
(T
A
=25°C,ƒ=1MHz)
Note: These parameters are calculated, not measured.
Parameter
Input Capacitance
Output Capacitance
CS1~4, WE1~4
(1)
Other Inputs
Symbol
C
IN1
C
IN2
C
OUT
Test Condition
V
IN
=0V
V
IN
=0V
V
OUT
=0V
typ
-
-
-
max Unit
20
22
22
pF
pF
pF
Notes: (1) On the PUMA 2E4001, 67E4001A, 77E4001A versions only.
2
ISSUE 4.2 : November 1998
PUMA 2/67/77E4001/A - 12/15/20
AC OPERATING CONDITIONS
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable Access Time
CS or OE to Output Float (2)
Output Hold from Address Change
12
Symnbol min max
t
RC
t
AA
t
CS
t
OE
t
DF
t
OH
120
-
-
0
0
0
-
120
120
60
60
-
15
min max
150
-
-
0
0
0
-
150
150
70
70
-
20
min
200
-
-
0
0
0
max Unit
-
200
200
80
80
-
ns
ns
ns
ns
ns
ns
Notes: (1) t
HZ
max. and t
OLZ
max. are measured with CL = 5pF, from the point when Chip Select or Output Enable return high
(whichever occurs first) to the time when the outputs are no longer driven. t
HZ
and t
OHZ
are shown for reference only:
they are characterized and not tested.
(2) This parameter is characterised and is not 100% tested.
Write Cycle
Parameter
Write Cycle Time
Address Set-up Time
Address Hold Time
Output Enable Set-up Time
Output Enable Hold Time
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width
Write Enable High Recovery
Data Set-up Time
Data Hold Time
Byte Load Cycle
Symbol
t
WC
t
AS
t
AH
t
OES
t
OEH
t
CS
t
CH
t
WP
t
WPH
t
DS
t
DH
t
BLC
min
-
0
50
0
0
0
0
100
50
50
0
-
typ
-
-
-
-
-
-
-
-
-
-
-
-
max
10
-
-
-
-
-
-
-
-
-
-
150
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 10ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* V
CC
=5V±10%
Output Test Load
I/O Pin
645
Ω
1.76V
100pF
3
ISSUE 4.2 : November 1998
PUMA 2/67/77E4001/A - 12/15/20
Data Polling Characterisitics (1)
Parameter
Data Hold Time
OE Hold Time
OE to Output Delay (2)
Write Recovery Time
Symbol
t
DH
t
OEH
t
OE
t
WR
min
10
10
-
0
typ
-
-
-
-
max
-
-
-
-
Unit
ns
ns
ns
ns
Notes: (1) These parameter are characterised and is not 100% tested.
(2) See AC Read Characteristics.
Toggle Bit Characteristics (1)
Parameter
Data Hold Time
OE Hold Time
OE to Output Delay (2)
OE High Pulse
Write Recovery Time
Symbol
t
DH
t
OEH
t
OE
t
OEHP
t
WR
min
10
10
-
150
0
typ
-
-
-
-
-
max
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
Notes: (1) These parameter are characterised and is not 100% tested.
(2) See AC Read Characteristics.
4
ISSUE 4.2 : November 1998
PUMA 2/67/77E4001/A - 12/15/20
AC Write Waveform - WE Controlled
t
WC
Address
t
AS
WE
t
AH
t
WP
t
WPH
t
CS
CS1~4
t
CH
t
OES
OE
t
OEH
DATA
t
DS
t
DH
AC Write Waveform - CS Controlled
t
WC
Address
t
AS
t
CS
WE
t
AH
t
CH
t
WP
CS1~4
t
OES
OE
t
WPH
t
OEH
DATA
t
DS
t
DH
5
FPGA/CPLD
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