CXA2061S
Y/C/RGB/D for NTSC Color TVs
Description
The CXA2061S is a bipolar IC which integrates
the luminance signal processing, chroma signal
processing, RGB signal processing, and sync and
deflection signal processing functions for NTSC
system color TVs onto a signal chip. The IC also
includes deflection processing functions for wide
TVs.
48 pin SDIP (Plastic)
Features
•
Reduction in peripheral parts
(ceramic oscillator, AKB sample-and-hold capacitor, etc.)
•
I
2
C bus compatible
•
Built-in deflection compensation circuit which is capable of supporting variaus wide modes
•
Non-adjusting V oscillator frequency with a countdown system
•
Non-interlace display support (even/odd selectable)
•
Non-adjusting Y/C filter
•
Three sets of CV inputs, two sets of Y/C inputs (can serve as both Y/C and CV inputs), one set of Y/C inputs
supports an external combfilter, two sets of RGB inputs, one set of YUV inputs
•
It can be outputted YUV on RGB1 inputs
•
Built-in dynamic picture and dynamic color circuits
•
Built-in AKB and gamma correction circuits
•
FSC output
Applications
Color TVs (4:3, 16:9)
Structure
Bipolar silicon monolithic IC
Abusolute Maximum Ratings
(Ta = 25°C, GND1, 2 = 0V)
•
Supply voltage
V
CC
1
,
2 –0.3 to +12
V
•
Operating temperature
Topr
–20 to +75
°C
•
Storage temperature
Tstg
–65 to +150
°C
•
Allowable power dissipation P
D
1.5
W
(when mounted on a 50mm
×
50mm board)
•
Voltages at each pin
–0.3 to V
CC
1
,
2 + 0.3 V
Operating Condition
Supply voltage
V
CC
1
,
2
9 ± 0.5
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97538-PS
Block Diagram
EY IN
R1 IN
YUV SW
G1 IN
B2 IN (B-YOUT)
30
29
X'tal
APED
GND2
Y CLAMP
B1 IN
V
CC
2
APC FIL
EB-Y IN
YS1
FSCOUT
ER-Y IN
R2 IN (YOUT)
45
47
44
15
25
8
38
28
26
46
40
1
39
36
31
27
32
37
FSC
<FSC SW>
EYUV CLAMP
YUV SW
<YSEL>
YUVOUT
<YUVOUT>
CLAMP
RGB 1/2
ABL/PEAK LIM
<ABL MODE>
<ABL VTH>
AKB
<<IKR>>
VM OUT/
V PROT
G2 IN (R-YOUT)
YS2/YM
42 ABL FIL
3 ABL IN
21 IK IN
APC
<HUE>
C VCO
DEMOD.
DPIC
<DPIC>
<AGING>
COLOR AMP
<COLOR>
<C OFF>
AXIS
<AXIS NTSC>
<AXIS PAL>
24 B OUT
23 G OUT
22 R OUT
ACC DET.
Y/C MIX
RGB CLAMP
ACC AMP
BPF
<C BPF>
FILTER ALIGNMENT
CAL. by fsc
CLAMP
DC TRAN
<DC TRAN>
YS1 SW
<RGB SEL>
YM SW
YS2 SW
DYNAMIC COLOR
<DYNAMIC C>
PICTURE AMP
<PICTURE>
GAMMA AMP
<GAMMA>
CLAMP
BRIGHT CONT.
<BRIGHT>
DRIVE AMP
<R/G/B DRIVE>
CUTOFF CONT.
<R/G/B CUTOFF>
R/G/B BLK
<PON>
<R/G/B ON>
CHROMA
AMP
COLOR KILLER
<<KILLER ID OFF>>
SCP
HD
REG
V TIM
AFC FIL
HP/
HPROTECT
GND1
I REF
V
CC
1
–2–
TRAP + EQ
<TRAP OFF>
SHARPNESS DL
SHARPNESS AMP
<SHARPNESS>
<SHP F0>
<PRE/OVER>
WIDE SAW FUNC.
COUNT DOWN
<CD MODE>
<INTERLACE>
LINE COUNTER
V TIM GEN.
<V UNDER SCAN>
VSAW GEN.
VTIM
<ASPECT>
<SCROLL>
<UPPER VLIN>
<LOWER VLIN>
<V ZOOM>
<V UNDER SCAN>
AFC
<AFC GAIN>
<FH HIGH>
<<HLOCK>>
<<HCENT>>
HSAW GEN.
<HOSC>
(ZAP)
H TIM GEN.
<H BLK>
<LEFT HBLK>
<RIGHT HBLK>
PHASE DET.
<H POSITION>
<AFC BOW>
<AFC AMGLE>
HPROT
<<HNG>>
20
17
5
18
CHROMA
DAC
SW
VPROT
<<VNG>>
VM AMP
(OFF YS/YM)
I
2
C BUS
DECODER
STATUS I/F
35 SDA
34 SCL
TV/C2 IN 43
CHROMA SW
ATT
14 VD–
13 VD+
C1 IN 2
VD SAW FUNC.
<VON>
<S CORRECTION>
<V SIZE>
<V LINEARITY>
<V POSITION> <EHT COMP>
CVBS2/Y2 IN 41
Y SW
Y
CVBS1/Y1 IN 4
COMB-C IN 7
MONITOR SW
V SYNC SEP
<VSS>
EW PARABOLA FUNC.
<H SIZE>
<TRAPEZIUM>
<PIN AMP>
<EW DC>
<CORNERPIN>
11 EW
COMB-Y IN 9
VIDEO SW
H SYNC SEP
<HSS>
<H MASK>
MON OUT 6
HD GEN.
IREF REG
<HD W>
<VIDEO SEL>
<S SEL>
19
10
12
16
33
CXA2061S
CXA2061S
Pin Configuration
APED 1
C1 IN 2
ABL IN 3
CVBS1/Y1 IN 4
V TIM 5
MON OUT 6
COMB-C IN 7
Y CLAMP 8
COMB-Y IN 9
GND1 10
EW 11
I REF 12
VD+ 13
VD– 14
VM OUT/V PROT 15
REG 16
SCP 17
HP/PROTECT 18
HD 19
AFC FIL 20
IK IN 21
R OUT 22
G OUT 23
B OUT 24
48
47
46
45
44
NC
X'tal
FSCOUT
APC FIL
V
CC
2
43 TV/C2 IN
42
ABL FIL
41 CVBS2/Y2 IN
40
39
38
37
36
35
GND2
EB-Y IN
ER-Y IN
EY IN
YUV SW
SDA
34 SCL
33 V
CC
1
32
R2 IN
31 G2 IN
30
29
B2 IN
YS2/YM
28 R1 IN
27 G1 IN
26
B1 IN
25 YS1
–3–
CXA2061S
Pin Description
Pin
No.
Symbol
Equivalent circuit
Description
4µA
1k
1
1
APED
94k
Capacitor connection for black peak hold
of the dynamic picture (black expansion).
Connect to GND via a 4.7µF capacitor.
147
2
2
C1 IN
50k
5.4V
Chroma signal input. Input a chroma
signal with a burst level of 300mVp-p via a
0.1µF capacitor. The S terminal signal is
normally input.
147
3.7V / 1.7V
3
ABL IN
3
ABL control signal input and VD high
voltage fluctuation compensation signal
input. High voltage fluctuation
compensation has linear control
characteristics for the pin voltage range of
about 8 to 1V. Control characteristics can
be varied through EHT COMP control of
the bus. ABL function as PIC/BRT-ABL
(average value type). The threshhold
voltage at which ABL begins to have effect
can be switched between 3 to 1V by the
bus.
147
4
4
CVBS1/Y1 IN
50k
5.4V
CVBS signal/luminance signal input.
Input a 1Vp-p (100% white including sync)
CVBS signal via a 1µF capacitor.
When inputting Y/C separated signal,
input the Y signal.
–4–
CXA2061S
Pin
No.
Symbol
Equivalent circuit
Description
147
5
V TIM
5
25k
V timing pulse. V timing pulse, HSS and
VSS output can be selected by VTIM SEL
control of the bus.
200
25.1k
6
4K
6
MON OUT
The signal input from TV, CVBS1 and
CVBS2 are selected by VIDEO SEL and
S SEL of the bus and output. In the case
of S terminal input, the luminance signal
and chroma signal are mixed and output.
The output level is 2Vp-p including sync.
147
7
10p 25k
7
COMB-C IN
25k
5.4V
Input the chroma signal from the comb
filter. Standard input level (burst level) is
0.6Vp-p.
1.5k
8
8
Y CLAMP
Capacitor connection for luminance signal
clamp.
Connect to GND via a 0.1µF capacitor.
147
9
25k
9
COMB-Y IN
25k
5.4V
Input the luminance signal from the comb
filter. The signal is input via a 0.1µF
capacitor with a level of 2Vp-p.
(100% white including sync)
–5–