Exceeding the absolute maximum rating may damage the device.
The device is not guaranteed to function outside its operating rating.
Outputs loaded with 50Ω to ground.
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Condition
Min
2.0
Typ
Max
0.8
Units
V
V
µA
µA
+20
–250
–600
December 2009
4
M9999-121409-D
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89809L
AC Electrical Characteristics
(4)
T
A
= 0°C to +85°C, unless noted.
Symbol
t
PD
f
MAX
t
SKEW
t
SKPP
t
JITTER
V
PP
V
CMR
t
S
t
H
t
r
, t
f
Notes:
4.
5.
6.
7.
8.
9.
Outputs loaded with 50Ω to ground. Airflow
≥
300lfpm.
Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
Output swing greater than 450mV.
The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
The part-to-part skew is defined as the absolute worst-case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
The V
PP
(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
Parameter
Propagation Delay
(5)
Maximum Operating Frequency
(6)
Within-Device Skew
(7)
Part-to-Part Skew
(8)
Phase Noise(RMS)
Minimum Input Swing
LVPECL_CLK
(9)
Condition
Min
825
500
Typ
1050
Max
1275
50
200
Units
ps
MHz
ps
ps
ps
mV
12kHz-20MHz @ 500MHz
See Figure 3
600
–1.5
1.0
0.5
300
0.241
1
Common Mode Range
(10)
LVPECL_CLK
OE Set-Up Time
(11)
OE Hold Time
Output Rise/Fall Time
(20% to 80%)
–0.4
V
ns
ns
650
ps
10. V
CMR
is defined as the range within which the VIH level may vary with the device still meeting the propagation delay specification. The numbers in
the table are referenced to V
CCI
. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to V
PP
(min).
11. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH-to-LOW transition ensures outputs remain disabled during the next
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