1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Ratings” conditions
for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.
Ψ
JB
uses 4-layer
θ
JA
in still air unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Includes current through internal 50Ω pull-ups.
7. See “Operating Characteristics” section for V
IN
and V
DIFF_IN
definition.
Parameter
Power Supply
Power Supply Current
Differential Input Resistance
(IN-to-/IN)
Input Resistance
(IN-to-VT, /IN-to-VT)
Input High Voltage (IN, /IN)
Input Low Voltage (IN, /IN)
Input Voltage Swing (IN, /IN)
Differential Input Voltage Swing
|IN - /IN|
Voltage from Input to V
T
Condition
Min
3.0
Typ
3.3
66
Max
3.6
88
120
60
V
CC
V
IH
–0.1
V
CC
Units
V
mA
Ω
Ω
V
V
V
V
No Load, Max. V
CC(6)
80
40
1.2
0
Notes 7
Notes 7
0.1
0.2
100
50
1.8
V
M9999-041608
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY89543L
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS
(9)
V
CC
= 3.3V
±10%;
T
A
= –40°C to +85°C; R
L
= 100Ω across Q and /Q, unless otherwise stated.
Symbol
V
OH
V
OL
V
OUT
V
DIFF-OUT
V
OCM
∆V
OCM
Parameter
Output HIGH Voltage (Q, /Q)
Output LOW Voltage (Q, /Q)
Output Voltage Swing (Q, /Q)
Differential Output Voltage Swing
|Q - /Q|
Output Common Mode Voltage
(Q, /Q)
Change in Common Mode Voltage
(Q, /Q)
Condition
See Figure 5a
See Figure 5a
See Figures 1a, 5a
See Figure 1b
See Figure 5b
See Figure 5b
0.925
250
500
1.125
–50
350
700
1.275
+50
Min
Typ
Max
1.475
Units
V
V
mV
mV
V
mV
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
(9)
V
CC
= 3.3V
±10%;
T
A
= –40°C to +85°C; unless otherwise stated.
Symbol
V
IH
V
IL
I
IH
I
IL
Note:
9. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Condition
Min
2.0
Typ
Max
V
CC
0.8
40
–300
Units
V
V
µA
µA
M9999-041608
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge
®
SY89543L
AC ELECTRICAL CHARACTERISTICS
(10)
V
CC
= 3.3V
±10%;
T
A
= –40°C to +85°C; R
L
= 100Ω across Q and /Q, unless otherwise stated.
Symbol
f
MAX
t
PD
t
SKEW
Parameter
Maximum Operating Frequency
V
OUT
> 200mV
Differential Propagation Delay
IN-to-Q
SEL-to-Q
Input-to-Input Skew
Channel-to-Channel Skew
Part-to-Part Skew
t
JITTER
Data
Random Jitter (RJ)
Deterministic Jitter (DJ)
Clock
Total Jitter (TJ )
Cycle-to-Cycle Jitter
Crosstalk-Induced Jitter
t
R
, t
F
Notes:
10. Measured with 100mV input swing. See “Timing Diagrams ” section for definition of parameters. High-frequency AC-parameters are guaranteed by
design and characterization.
11. Input-to-input skew is the difference in time from an input-to-output in comparison to any other input-to-output. In addition, the input-to-input skew
does not include the output skew.
12. Channel-to-channel skew is measured between two different outputs under identical conditions.
13. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs. Total skew is calculated as the RMS (Root Mean Square) of the input skew and output skew.
14. RJ is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 3.2Gbps.
15. DJ is measured at 1.25Gbps and 3.2Gbps, with both K28.5 and 2
23
–1 PRBS pattern.
16. Total jitter definition: with an ideal clock input of frequency
≤f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than the
specified peak-to-peak jitter value.
17. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn-Tn-1 where T is the time between rising edges of the output
signal.
18. Crosstalk is measured at the output while applying two similar frequencies to adjacent inputs that are asynchronous with respect to each other at the
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FPGA/CPLD
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