SY89546U
2.5V, 3.2Gbps Differential 4:1 LVDS
Multiplexer with 1:2 Fanout and Internal
Termination
General Description
The SY89546U is a precision, High-speed 4:1 differential
multiplexer that provides two copies of the selected input.
The high speed LVDS (350mV) compatible outputs with a
guaranteed throughput of up to 3.2Gbps over temperature
and voltage.
The SY89546U differential inputs include Micrel’s unique
3-pin internal termination design that allows access to the
termination network through a VT pin. This feature allows
the device to easily interface to different logic standards,
both AC- and DC-coupled without external resistor-bias
and termination networks. The result is a clean, stub-free,
low jitter interface solution.
The SY89546U operates from a single 2.5V supply, and is
guaranteed over the full industrial temperature range
(–40°C to +85°C). For applications that require a 3.3V
supply, consider the SY89547L. Or, for applications that
only require one differential output, consider the
SY89544U or SY89545L. The SY89546U is part of
Micrel’s Precision Edge® product family.
Data sheets and support documentation can be found on
Micrel’s web site at:
www.micrel.com.
Features
•
Selects among four differential inputs
•
Provides two copies of the selected input
•
Guaranteed AC parameters over temp/voltage:
– DC-to>3.2Gbps data rat throughput
– <620ps In-to-Out t
pd
– <150ps t
r
/t
f
time
•
Unique input isolation design minimize crosstalk
•
Ultra-low jitter design:
– <1ps
RMS
random jitter
– <10ps
PP
deterministic jitter
– <10ps
PP
total jitter (clock)
– <0.7ps
RMS
corsstalk-induced jitter
•
Internal input termination
•
Unique input termination and VT pin accepts DC-
coupled and AC-coupled inputs (LVDS, LVPECL,
CML)
•
350mV LVDS output swing
•
Power supple 2.5V ±5%
•
–40°C to +85°C temperature range
•
Availabe in 32-pin (5mmx5mm) MLF® package
Applications
•
SONET/SDH multi-channel select applications
•
Fibre Channel applications
•
GigE application
___________________________________________________________________________________________________________
Typical Performance
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
April 2011
M9999-041911-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89546U
Functional Block Diagram
April 2011
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Micrel, Inc.
SY89546U
Ordering Information
(1)
Part Number
SY89546UMI
SY89546UMITR
SY89546UMG
(3)
SY89546UMGTR
(2,3)
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Recommended for new designs.
2)
Package Type
MLF-32
MLF-32
MLF-32
MLF-32
Operating Range
Industrial
Industrial
Industrial
Industrial
Package Marking
SY89546U
SY89546U
SY89546U with Pb-Free
bar-line indicator
SY89546U with Pb-Free
bar-line indicator
Lead Finish
Sn-Pb
Sn-Pb
Pb_Free
NiPdAu
Pb_Free
NiPdAu
Pin Configuration
32-Pin MLF®
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Micrel, Inc.
SY89546U
Pin Description
Pin Number
4, 2, 21, 32,
30, 27, 25,
23, 21
Pin Name
IN0, /IN0
IN1, /IN1
IN2, /IN2
IN3, /IN3
3, 31, 26, 22
VT0, VT1,
VT2, VT3
6, 19
SEL0, SEL1
Pin Function
Differential Inputs: These inputs pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to
a V
T
pin through 50Ω. Note that these inputs will default to an indeterminate state if left open.
Unused differential input pairs can be terminated by connecting one input to V
CC
and the
complementary input to GND through a 1kΩ resistor. The VT pin is to be left open in this
configuration. Please refer to the “input Interface Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair, terminates to a V
T
pin.
The V
TA0
, V
TA1
, V
TB0
, V
TB1
pins provide a center-tap to a termination network for maximum
interface flexibility. See “input Interface Applications” section for more details.
These single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexers. Note
that these inputs are internally connected to a 25kΩ pull-up resistor and will default to a logic
HIGH state if left open. Input switching threshold is V
CC
/2.
Positive Power Supply: Bypass with 0.1μF║ 0.01μF low ESR capacitors.
1, 5, 8, 17,
20, 24, 28,
29
10, 11, 14,
15
VCC
Q0, /Q0
Q1, /Q1
GND,
Exposed pad
Differential Outputs: These LVDS outputs pairs are the outputs of the device. They are a logic
function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to the “Truth
Table” for details. If an output is not used, it must be terminated with 100Ω across the
differential pair.
Ground: Ground pin and exposed pad must be connected to the same ground plane.
7, 9, 12, 13,
16, 18
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Micrel, Inc.
SY89546U
Absolute Maximum Ratings
(1)
Supply Voltage (V
cc
) ..................................... –0.5V to +4.0V
Input Voltage (V
IN
)
....................................................................
–0.5V to V
cc
Termination Current
(3)
Source or sink current on VT............................±100mA
Input Current
Source or sink current on VT..............................±50mA
Lead Temperature (soldering, 20sec.)..................... +260°C
Storage Temperature (Ts).........................–65°C to +150°C
Operating Ratings
(2)
Supply Voltage (V
CC
)............................. 2.375V to 2.625V
Ambient Temperature (T
A
).......................–40°C to +85°C
Package Thermal Resistance
(4)
MLF® (θ
JA
)
Still Air, multi-layer PCB .................................35°C/W
500lfpm, multi-layer PCB................................28°C/W
MLF® (Ψ
JA
)
Junction-to-Board ...........................................20°C/W
DC Electrical Characteristics
(5)
-40°C≤ T
A
≤
+85°C, unless stated otherwise.
Symbol
V
CC
I
CC
R
DIFF_IN
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
IN-to-V
T
Notes:
1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Ratings” conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential (GND) on the PCB.
Ψ
JA
uses
4-layer
θ
JA
in still-air unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Includes current through internal 50Ω pull-ups.
7. See “Single-Ended and Differential Swings” section for V
IN
and V
DIFF_IN
definition.
Parameter
Power Supply
Power Supply Current
Differential Input Resistance
(IN-to-/IN)
Input Resistance
(IN-to-V
T
, /IN-to-V
T
)
Input High Voltage
(IN, /IN)
Input Low Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
|IN – /IN|
Condition
No Load, Max. V
CC(6)
Min
2.375
80
40
1.2
0
Note 7
Note 7
0.1
0.2
Typ
2.5
75
100
50
Max
2.625
100
120
60
V
CC
V
IH
-0.1
V
CC
Units
V
mA
Ω
Ω
V
V
V
V
Note 7
1.8
V
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