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SY10E111AEJYTR: 产品描述5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER; 产品类别逻辑逻辑; 文件大小149KB，共7页; 制造商Microchip(微芯科技); 官网地址https://www.microchip.com; 标准

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SY10E111AEJYTR概述

5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER

SY10E111AEJYTR规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	Microchip(微芯科技)
零件包装代码	QLCC
包装说明	QCCJ,
针数	28
Reach Compliance Code	compli
系列	10E
输入调节	DIFFERENTIAL
JESD-30 代码	S-PQCC-J28
JESD-609代码	e3
长度	11.48 mm
逻辑集成电路类型	LOW SKEW CLOCK DRIVER
湿度敏感等级	2
功能数量	1
反相输出次数
端子数量	28
实输出次数	9
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	QCCJ
封装形状	SQUARE
封装形式	CHIP CARRIER
峰值回流温度（摄氏度）	260
传播延迟（tpd）	0.73 ns
认证状态	Not Qualified
Same Edge Skew-Max（tskwd）	0.05 ns
座面最大高度	4.37 mm
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.75 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	ECL
温度等级	INDUSTRIAL
端子面层	Matte Tin (Sn)
端子形式	J BEND
端子节距	1.27 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	11.48 mm

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Micrel, Inc.

5V/3.3V 1:9 DIFFERENTIAL

CLOCK DRIVER (w/ENABLE)

SY10E111AE/LE

SY100E111AE/LE

Precision Edge

SY10E111AE/LE

Precision Edge

SY100E111AE/LE

FEATURES

■

5V and 3.3V power supply options

■

200ps part-to-part skew

■

50ps output-to-output skew

■

Differential design

output

Enable Input

Voltage and temperature compensated outputs

Precision Edge

DESCRIPTION

The SY10/100E111AE/LE are low skew 1-to-9 differential

drivers designed for clock distribution in mind. The SY10/

100E111AE/LE's function and performance are similar to

the popular SY10/100E111, with the improvement of lower

jitter and the added feature of low voltage operation. It

accepts one signal input, which can be either differential or

single-ended if the V

output is used. The signal is fanned

out to 9 identical differential outputs. An enable input is

also provided such that a logic HIGH disables the device by

forcing all Q outputs LOW and all Q outputs HIGH.

The E111AE/LE is specifically designed, modeled and

produced with low skew as the key goal. Optimal design

and layout serve to minimize gate to gate skew within a

device, and empirical modeling is used to determine process

control limits that ensure consistent t

distributions from

lot to lot. The net result is a dependable, guaranteed low

skew device.

To ensure that the tight skew specification is met it is

necessary that both sides of the differential output are

terminated into 50Ω, even if only one side is being used. In

most applications, all nine differential pairs will be used

and therefore terminated. In the case where fewer that

nine pairs are used, it is necessary to terminate at least the

output pairs on the same package side as the pair(s) being

used on that side, in order to maintain minimum skew.

Failure to do this will result in small degradations of

propagation delay (on the order of 10-20ps) of the output(s)

being used which, while not being catastrophic to most

designs, will mean a loss of skew margin.

The E111AE/LE, as with most other ECL devices, can

be operated from a positive V

supply in PECL mode.

This allows the E111AE/LE to be used for high performance

clock distribution in +5V/+3.3V systems. Designers can

take advantage of the E111AE/LE's performance to

distribute low skew clocks across the backplane or the

board. In a PECL environment, series or Thevenin line

terminations are typically used as they require no additional

power supplies. For systems incorporating GTL, parallel

termination offers the lowest power by taking advantage of

the 1.2V supply as terminating voltage.

■

75K

Ω

input pulldown resistors

■

Fully compatible with Motorola MC10/100E111

■

Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN NAMES

IN, IN

, Q

— Q

, Q

CCO

Function

Differential Input Pair

Enable Input

Differential Outputs

Output

to Output

Precision Edge is a registered trademark of Micrel, Inc.

M9999-030509

hbwhelp@micrel.com or (408) 955-1690

Rev.: K

Amendment: /0

March 2009

Rev. Date:

SY10E111AEJYTR

SY10E111AEJYTR概述

SY10E111AEJYTR规格参数

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