SM843256
10 Gigabit Ethernet and SONET, 6 output,
Ultra-Low Jitter LVPECL Frequency
Synthesizer
General Description
The SM843256 provides a low-noise timing solution for
high speed, high accuracy synthesis of clock signals.
Common applications include SONET, Gigabit Ethernet,
10 Gigabit Ethernet, and similar networking standards. It
includes a unique power reduction methodology, along
with a patented RotaryWave
TM
architecture that provides a
very stable clock with very low noise.
Power supplies of either 3.3V or 2.5V are supported, with
superior jitter and phase noise performance. The device
synthesizes different low noise LVPECL output
frequencies such as 125MHz, 156.25MHz, 312.5MHz, and
625MHz for Ethernet applications; 77.76MHz, 155.52MHz,
311.04MHz, and 622.08MHz for SONET applications. The
crystal reference frequencies used include 25MHz and
19.44Mhz for Ethernet and SONET applications,
respectively.
The SM843256 is an excellent replacement for IDT Femto-
clocks, with improved accuracy, power consumption,
waveform integrity, and jitter.
Data sheets and support documentation can be found on
Micrel’s web site at:
www.micrel.com.
Features
•
Generates six LVPECL outputs
•
2.5V or 3.3V operating range
•
Typical phase jitter @ 156.25MHz
(1.875MHz to 20MHz): 80fs (typical) @ 3.3V
•
75MHz to 625MHz output frequencies
•
Industrial temperature range
•
Green, RoHS, and PFOS compliant
•
Available in 24-pin TSSOP EPAD
•
Operating supply modes:
Core/Output
3.3V/3.3V, 3.3V/2.5V, 2.5V/2.5V
Applications
•
•
•
•
SONET
Gigabit Ethernet
10-Gigabit Ethernet
Infiniband
________________________________________________________________________________________________________________________
Block Diagram
RotaryWave is a trademark of Multigig, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
July 2010
M9999-072110-B
Micrel, Inc.
SM843256
Ordering Information
(1, 2)
Part Number
SM843256KA
Notes:
1. Devices are Green, RoHS, and PFOS Compliant.
2. Lead finish is 100% matte tin.
Marking
843256
Shipping
Tube, Tape & Reel
Junction Temperature Range
–40° to +85°C
Package
24-Pin TSSOP EPAD
Pin Configuration
24-Pin TSSOP EPAD
(Top View)
July 2010
2
M9999-072110-B
Micrel, Inc.
SM843256
Pin Description
Pin Number
1, 2
3, 4
5, 6
7, 8
9
10
11
12
13
14
15
16, 17
18
19, 20
21, 22
23, 24
Pin Name
V
DDO
/Q2, Q2
/Q1, Q1
/Q0, Q0
PLL_BYPASS
V
DDA
V
DD
FB_SEL
XTAL_IN
XTAL_OUT
N_SEL0
GND
N_SEL1
/Q5, Q5
/Q4, Q4
/Q3, Q3
Pin Type
PWR
O, (DIF)
O, (DIF)
O, (DIF)
I, (SE)
PWR
PWR
I, (SE)
I, (SE)
O, (SE)
I, (SE)
PWR
I, (SE)
O, (DIF)
O, (DIF)
O, (DIF)
LVCMOS
LVPECL
LVPECL
LVPECL
LVCMOS
12pF crystal
12pF crystal
LVCMOS
LVPECL
LVPECL
LVPECL
LVCMOS
Pin Level
Pin Function
2.5V or 3.3V Power Supply
Differential Clock Output
Differential Clock Output
Differential Clock Output
Pull-Up 45k, Single-Ended Input Select Pin.
Logic (0) = PLL Output
Logic (1) = Xtal Reference
Analog 3.3V or 2.5V Power Supply
3.3V or 2.5V Power Supply
Pull-Down 45k, Single-Ended Input Select Pin
Crystal Reference Input, no load caps needed.
Crystal Reference Output, no load caps needed.
Pull-Up 45k, Single-Ended Input Select Pin
Ground
Pull-Up 45k, Single-Ended Input Select Pin
Differential Clock Output
Differential Clock Output
Differential Clock Output
Input and Output Frequency Table
X
TAL
(MHz)
24
24
24
24
25
25
25
25
18.75
18.75
18.75
18.75
19.44
19.44
19.44
19.44
19.53125
19.53125
19.53125
19.53125
FB_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
N_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
N_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs (MHz)
600
300
150
120
625
312.50
156.25
125
600
300
150
75
622.08
311.04
155.52
77.76
625
312.5
156.25
78.125
Application
-
-
SAS/SATA
-
10 Gigabit Ethernet
10 Gigabit Ethernet
10 Gigabit Ethernet
Gigabit Ethernet/Infiniband/PCI/PCI-E/PCI-X
-
-
SAS/SATA
SAS/SATA
10 Gigabit Ethernet/SONET
SONET
SONET
SONET
10 Gigabit Ethernet
10 Gigabit Ethernet
10 Gigabit Ethernet
10 Gigabit Ethernet
July 2010
3
M9999-072110-B
Micrel, Inc.
SM843256
Absolute Maximum Ratings
(1)
Supply Voltage (V
DDA
, V
DD
, V
DDO
)................................+4.6V
Input Voltage (V
IN
)………………………-0.50V to V
DD
+0.5V
LVPECL Output Current ( I
OUT
)
Continuous……………………………………………….50mA
Surge…………………………………………………….100mA
Lead Temperature (soldering, 20sec.)....................... 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (T
s
) ..........................-65°C to +150°C
Operating Ratings
(2)
Supply Voltage (V
DDO
) .......................... +2.375V to +3.465V
Supply Voltage (V
DD,
V
DDA
) ................... +2.375V to +3.465V
Ambient Temperature (T
A
) .......................... –40°C to +85°C
(3)
Junction Thermal Resistance
TSSOP (θ
JA
)(Still Air).........................................32°C/W
DC Electrical Characteristics
(4)
V
DDA
= V
DD
= 3.3V ±5% or 2.5V ±5%, V
DDO
= 2.5V ±5%, T
A
= –40°C to +85°C, unless noted.
Symbol
V
DDO
V
DDA
,V
DD
I
DDA
I
DD
I
DDO
Parameter
2.5V Operating Voltage
3.3V Operating Voltage
Analog Supply Range
Core Supply Current
I/O Supply Range
F
OUT
= 156.25MHz
F
OUT
= 625.00MHz
F
OUT
= 156.25MHz
F
OUT
= 625.00MHz
F
OUT
= 156.25MHz
F
OUT
= 625.00MHz
Condition
Min
2.375
2.375
Typ
2.5
3.3
55
56
13
13
235
330
TBD
mA
17
mA
Max
2.625
3.465
65
Units
V
V
mA
V
DDA
= V
DD
= V
DDO
= 3.3V ±5%, T
A
= –40°C to +85°C, unless noted.
Symbol
V
DDA
,
V
DD
,
V
DDO
I
DDA
I
DD
I
DDO
Parameter
3.3V Operating Voltage
Condition
Min
3.135
Typ
3.3
Max
3.465
Units
V
Analog Supply Range
Core Supply Current
I/O Supply Range
F
OUT
= 156.25MHz
F
OUT
= 625.00MHz
F
OUT
= 156.25MHz
F
OUT
= 625.00MHz
F
OUT
= 156.25MHz
F
OUT
= 625.00MHz
55
56
13
13
256
366
65
17
282
mA
mA
mA
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
July 2010
4
M9999-072110-B
Micrel, Inc.
SM843256
LVPECL DC Electrical Characteristics
(5, 6)
V
DDA
= V
DD
= 3.3V ±5% or 2.5V ±5%, V
DDO
= 2.5V or 3.3V ±5%, T
A
= –40°C to +85°C, unless noted.
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage
Output Low Voltage
Peak-to-Peak Output Voltage Swing
Condition
50Ω to V
DDO
-2V
50Ω to V
DDO
-2V
Figure 1
Min
V
DDO
–1.145
V
DDO
–1.945
0.6
Typ
V
DDO
–0.97
V
DDO
–1.77
0.8
Max
V
DDO
–0.845
V
DDO
–1.645
1.0
Units
V
V
V
LVCMOS DC Electrical Characteristics
(6)
V
DDA
= V
DD
= 3.3V ±5% or 2.5V ±5%, V
DDO
= 2.5V or 3.3V ±5%, T
A
= –40°C to +85°C, unless noted.
Symbol
V
IH
V
IL
I
IH
I
IH
I
IL
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current (FB_SEL)
Input High Current (PLL_BYPASS),
(N_SEL0), (NSEL1)
Input Low Current (FB_SEL)
Input Low Current (PLL_BYPASS),
(N_SEL0), (NSEL1)
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Condition
Min
2
-0.3
Typ
Max
V
DD
+0.3
0.8
150
5
Units
V
V
μA
μA
μA
μA
AC Electrical Characteristics
(7)
V
DDA
= V
DD
= 3.3V ±5% or 2.5V ±5%, V
DDO
= 2.5V or 3.3V ±5%, T
A
= –40°C to +85°C, unless noted.
Symbol
F
OUT
T
R
/T
F
ODC
T
SKEW
T
LOCK
T
jit
(∅)
Parameter
Output Frequency
LVPECL Output Rise/Fall Time
Output Duty Cycle
Output-to-Output Skew
PLL Lock Time
RMS Phase Jitter (Output = 156.25 MHz)
Integration Range (12kHz – 20MHz)
Integration Range (1.875MHz – 20MHz)
Notes:
5. See Figure 4 for load test circuit example.
6. The circuit is designed to meet the DC specifications shown in the above table(s) after thermal equilibrium has been established.
7. The circuit is designed to meet the AC specifications shown in the above table(s) after thermal equilibrium has been established.
8. Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at the output differential crossing points.
Condition
Refer to Frequency Table
20% – 80%
Note 8
Min
75
100
46
Typ
175
50
Max
625
350
54
45
20
Units
MHz
ps
%
ps
ms
fs
fs
251
80
July 2010
5
M9999-072110-B
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