Freescale Semiconductor
Technical Data
DATA SHEET
MPC92432
Rev 2, 06/2005
1360 MHz Dual Output LVPECL
1360 MHz Dual
Clock Synthesizer
Output LVPECL Clock
MPC92432
Synthesizer
MPC92432
The MPC92432 is a 3.3 V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance
telecom, networking, and computing applications. With output frequencies from
21.25 MHz to 1360 MHz and the support of two differential PECL output signals,
the device meets the needs of the most demanding clock applications.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
21.25 MHz to 1360 MHz synthesized clock output signal
Two differential, LVPECL-compatible high-frequency outputs
Output frequency programmable through 2-wire I
2
C bus or parallel interface
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS compatible reference clock input
Synchronous clock stop functionality for both outputs
LOCK indicator output (LVCMOS)
LVCMOS compatible control inputs
Fully integrated PLL
3.3-V power supply
48-lead LQFP
48-lead Pb-free package available
SiGe Technology
Ambient temperature range: –40°C to +85°C
1360 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
FA SUFFIX
(1)
48-LEAD LQFP PACKAGE
CASE 932-03
AE SUFFIX
(2)
48-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 932-03
Applications
• Programmable clock source for server, computing, and telecommunication systems
• Frequency margining
• Oscillator replacement
Functional Description
The MPC92432 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a high-
frequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can
be changed on the fly for frequency margining purpose.
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS
compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a
selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2720 MHz. Its output
is scaled by a divider that is configured by either the I
2
C or parallel interfaces. The crystal oscillator frequency f
XTAL
, the PLL pre-
divider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is
internal.
The PLL post-divider N is configured through either the I
2
C or the parallel interfaces, and can provide one of six division ratios
(2, 4, 8, 16, 32, 64). This divider extends the performance of the part while providing a 50% duty cycle. The high-frequency out-
puts, Q
A
and Q
B
, are differential and are capable of driving a pair of transmission lines terminated 50
Ω
to V
CC
– 2.0 V. The second
high-frequency output, Q
B
, can be configured to run at either 1x or 1/2x of the clock frequency or the first output (Q
A
). The positive
supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise
induced jitter.
The configuration logic has two sections: I
2
C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB,
and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I
2
C
interface. The serial interface is I
2
C compatible and provides read and write access to the internal PLL configuration registers.
The lock state of the PLL is indicated by the LVCMOS-compatible LOCK output.
1. FA suffix: leaded terminations.
2. AE suffix: lead-free, EPP and RoHS-compliant.
IDT™
1360 MHz Dual Output LVPECL Clock Synthesizer
MPC92432
© Freescale Semiconductor, Inc., 2005. All
acquired by Integrated Device Technology, Inc
Freescale Timing Solutions Organization has been
rights reserved.
1
MPC92432
1360 MHz Dual Output LVPECL Clock Synthesizer
NETCOM
REF_CLK
XTAL1
XTAL2
REF_SEL
TEST_EN
SDA
SCL
ADR[1:0]
PLOAD
M[9:0]
NA[2:0]
NB
P
CLK_STOPx
BYPASS
MR
XTAL
f
REF
÷P
PLL
f
VCO
÷NA
f
QA
QA
f
QB
÷NB
QB
÷M
PLL
Configuration
Registers
I
2
C Control
LOCK
Figure 1. MPC92432 — Generic Logic Diagram
TEST_EN
25
24
23
22
21
20
36
35
34
33
32
31
30
29
28
27
GND
NA2
NA1
NA0
PLOAD
V
CC
MR
SDA
SCL
ADR1
ADR0
P
LOCK
26
GND
GND
V
CC
V
CC
V
CC
QA
QA
QB
QB
NB
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
M9
M8
M7
M6
M5
GND
M4
M3
M2
M1
M0
V
CC
MPC92432
19
18
17
16
15
14
13
CLK_STOPA
CLK_STOPB
It is recommended to use an external
RC filter for the analog V
CC_PLL
supply
pin. Please see the application section
for details.
V
CC
V
CC
BYPASS
V
CC_PLL
REF_SEL
REF_CLK
XTAL1
Figure 2. 48-Lead Package Pinout (Top View)
MPC92432
IDT™
1360 MHz Dual Output LVPECL Clock Synthesizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
2
2
XTAL2
GND
GND
MPC92432
Advanced Clock Drivers Devices
Freescale Semiconductor
MPC92432
1360 MHz Dual Output LVPECL Clock Synthesizer
NETCOM
Table 1. Signal Configuration
Pin
XTAL1, XTAL2
REF_CLK
REF_SEL
QA
QB
LOCK
M[9:0]
NA[2:0]
NB
P
P_LOAD
SDA
SCL
ADR[1:0]
BYPASS
TEST_EN
CLK_STOPx
MR
GND
V
CC_PLL
V
CC
I/O
Input
Input
Input
Output
Output
Output
Input
Input
Input
Input
Input
I/O
Input
Input
Input
Input
Input
Input
Supply
Supply
Supply
Analog
LVCMOS
LVCMOS
Differential LVPECL
Differential LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
CC
V
CC
Type
Crystal oscillator interface
PLL external reference input
Selects the reference clock input
High frequency clock output
High frequency clock output
PLL lock indicator
PLL feedback divider configuration
PLL post-divider configuration for output QA
PLL post-divider configuration for output QB
PLL pre-divider configuration
Selects the programming interface
I
2
C data
I
2
C clock
Selectable two bits of the I
2
C slave address
Selects the static circuit bypass mode
Factory test mode enable. This input must be set to logic low level in all
applications of the device.
Output Qx disable in logic low state
Device master reset
Negative power supply
Positive power supply for the PLL (analog power supply). It is recommended to
use an external RC filter for the analog power supply pin V
CC_PLL
.
Positive power supply for I/O and core
Function
IDT™
1360 MHz Dual Output LVPECL Clock Synthesizer
MPC92432
MPC92432
3
Advanced Clock Drivers Devices
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Freescale Semiconductor
3
MPC92432
1360 MHz Dual Output LVPECL Clock Synthesizer
NETCOM
Table 2. Function Table
Control
Inputs
REF_SEL
M[9:0]
NA[2:0]
NB
P
PLOAD
1
01 1111 0100b
(2)
010
0
1
0
Selects REF_CLK input as PLL reference clock
Selects the XTAL interface as PLL reference clock
Default
(1)
0
1
PLL feedback divider (10-bit) parallel programming interface
PLL post-divider parallel programming interface. See
Table 9
PLL post-divider parallel programming interface. See
Table 10
PLL pre-divider parallel programming interface. See
Table 8
Selects the parallel programming interface. The
Selects the serial (I
2
C) programming interface. The
internal PLL divider settings (M, NA, NB and P) are internal PLL divider settings (M, NA, NB and P) are
equal to the setting of the hardware pins. Leaving
set and read through the serial interface.
the M, NA, NB and P pins open (floating) results in a
default PLL configuration with f
OUT
= 250 MHz. See
application/programming section.
Address bit = 0
See
Programming the MPC92432
Address bit = 1
ADR[1:0]
SDA, SCL
BYPASS
00
1
PLL function bypassed
f
QA
= f
REF
÷ N
A
and
f
QB
= f
REF
÷ (N
A
· N
B
)
Application mode. Test mode disabled.
Output Qx is disabled in logic low state.
Synchronous disable is only guaranteed if NB = 0.
PLL function enabled
f
QA
= (f
REF
÷ P) · M ÷ N
A
and
f
QB
= (f
REF
÷ P) · M ÷ (N
A
· N
B
)
Factory test mode is enabled
Output Qx is synchronously enabled
TEST_EN
CLK_STOPx
MR
0
1
The device is reset. The output frequency is zero
The PLL attempts to lock to the reference signal.
and the outputs are asynchronously forced to logic The t
LOCK
specification applies.
low state.
After releasing reset (upon the rising edge of MR
and independent on the state of PLOAD), the
MPC92432 reads the parallel interface (M, NA, NB
and P) to acquire a valid startup frequency
configuration. See application/programming section.
Outputs
LOCK
PLL is not locked
PLL is frequency locked
1. Default states are set by internal input pull-up or pull-down resistors of 75 kΩ.
2. If f
REF
= 16 MHz, the default configuration will result in a output frequency of 250 MHz.
MPC92432
IDT™
1360 MHz Dual Output LVPECL Clock Synthesizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
4
4
MPC92432
Advanced Clock Drivers Devices
Freescale Semiconductor
MPC92432
1360 MHz Dual Output LVPECL Clock Synthesizer
NETCOM
Table 3. General Specifications
Symbol
V
TT
MM
HBM
LU
C
IN
θ
JA
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Input Capacitance
LQFP 48 Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
200
2000
200
4.0
69
64
53
50
TBD
TBD
Min
Typ
V
CC
– 2
Max
Unit
V
V
V
mA
pF
Inputs
Condition
°C/W
Natural convection
°C/W
200 ft/min
°C/W
Natural convection
°C/W
200 ft/min
°C/W
MIL-SPEC 883E
Method 1012.1
JESD 51-6, 2S2P multilayer test board
θ
JC
LQFP 48 Thermal Resistance Junction to Case
Table 4. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
(2)
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.9
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
Unit
V
V
V
mA
mA
°C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
2. All input pins including SDA and SCL pins.
IDT™
1360 MHz Dual Output LVPECL Clock Synthesizer
MPC92432
MPC92432
5
Advanced Clock Drivers Devices
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Freescale Semiconductor
5
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