Advance Information
MPC852TEC
Rev. 2.0, 12/2003
MPC852T
Hardware Specifications
This document contains detailed information for the MPC852T about power considerations,
DC/AC electrical characteristics, AC timing specifications, and pertinent electrical and
physical characteristics of the MPC852T. For information about functional characteristics of
the processor, refer to the
MPC866 PowerQUICC Family Users Manual
(MPC866UM). The
MPC852T contains a PowerPC
TM
processor core.
This document contains the following topics:
Topic
Section 1, “Overview”
Section 2, “Features”
Section 3, “Maximum Tolerated Ratings”
Section 4, “Thermal Characteristics”
Section 5, “Power Dissipation”
Section 6, “DC Characteristics”
Section 7, “Thermal Calculation and Measurement”
Section 9, “Power Supply and Power Sequencing”
Section 10, “Mandatory Reset Configurations”
Section 11, “Layout Practices”
Section 12, “Bus Signal Timing”
Section 13, “IEEE 1149.1 Electrical Specifications”
Section 14, “CPM Electrical Characteristics”
Section 15, “FEC Electrical Characteristics”
Section 16, “Mechanical Data and Ordering Information”
Section 17, “Document Revision History”
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1
Overview
The MPC852T PowerQUICC
TM
is a 0.18-micron derivative of the MPC860 PowerQUICC
family, and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The
MPC852T has a 1.8 V core and a 3.3 V I/O operation with 5-V TTL compatibility. The
MPC852T integrated communications controller is a versatile one-chip integrated
microprocessor and peripheral combination that can be used in a variety of controller
Features
applications. It particularly excels in Ethernet control applications, including CPE equipment, Ethernet
routers and hubs, VoIP clients, and WiFi access points.
The MPC852T is a PowerPC architecture-based derivative of the Motorola MPC860 Quad Integrated
Communications Controller (PowerQUICC). The CPU on the MPC852T is the MPC8xx core, a 32-bit
microprocessor that implements the PowerPC architecture, incorporating memory management units
(MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices.
2
Features
The MPC852T is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the
system integration unit (SIU), and the communication processor module (CPM). Figure 1 shows the
MPC852T block diagram.
The following list summarizes the key MPC852T features:
•
•
Embedded MPC8xx core up to 100 MHz
Maximum frequency operation of the external bus is 66 MHz
— The 50 MHz / 66 MHz core frequencies support both 1:1 and 2:1 modes.
— The 80 MHz / 100 MHz core frequencies support 2:1 mode only.
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution.
— 4-Kbyte data cache and 4-Kbyte instruction cache
– 4-Kbyte instruction cache is two-way, set-associative with 128 sets.
– 4-Kbyte data cache is two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces, and 16 protection groups
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory
devices
— DRAM controller-programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes–256 Mbytes)
•
•
•
•
2
MPC852T Hardware Specifications
MOTOROLA
Features
•
•
•
•
•
•
•
•
— Selectable write protection
— On-chip bus arbitration logic
Fast Ethernet Controller (FEC)
General-purpose timers
— Two 16-bit timers or one 32-bit timer
— Gate mode can enable or disable counting.
— Interrupt can be masked on reference match and event capture.
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Interrupts
— Seven external interrupt request (IRQ) lines
— Seven port pins with interrupt capability
— Eighteen internal interrupt sources
— Programmable priority between SCCs
— Programmable highest-priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example,
GRACEFUL STOP TRANSMIT
,
ENTER HUNT
MODE
, and
RESTART TRANSMIT
)
— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— 8 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Two baud rate generators
— Independent (can be connected to any SCC3/4 or SMC1)
— Allows changes during operation
— Autobaud support option
Two SCCs (serial communication controllers)
— Ethernet/IEEE 802.3 optional on SCC3 & SCC4, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Universal asynchronous receiver transmitter (UART)
— Totally transparent (bit streams)
— Totally transparent (frame-based with optional cyclic redundancy check (CRC))
One SMC (serial management channels)
MPC852T Hardware Specifications
3
MOTOROLA
Features
•
•
•
•
•
— UART
One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports one independent PCMCIA socket; 8-memory or I/O windows supported
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: =
≠
< >
— Each watchpoint can generate a break point internally.
Normal high and normal low power modes to conserve power
1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of the
5-V Tolerant pins.
4-Kbyte
Instruction
Instruction Cache
Bus
System Interface Unit (SIU)
Unified
Bus
Memory Controller
Internal
External
Bus Interface Bus Interface
Unit
Unit
System Functions
PCMCIA-ATA Interface
Embedded
MPC8xx
Processor
Core
Instruction MMU
32-Entry ITLB
Load/Store
Bus
4-Kbyte
Data Cache
Data MMU
32-Entry DTLB
Fast Ethernet
Controller
DMAs
FIFOs
10/100
Base-T
Media Access
Control
Parallel I/O
2 Baud Rate
Generators
2
Interrupt
8-Kbyte
Timers
Controllers Dual-Port RAM
32-Bit RISC Controller
and Program
ROM
Timers
1 Virtual
IDMA
&
8 Serial
DMA
Channels
MII
SCC3
SCC4
SMC1
SPI
Serial Interface (NMSI)
Figure 1. MPC852T Block Diagram
4
MPC852T Hardware Specifications
MOTOROLA
Maximum Tolerated Ratings
3
Maximum Tolerated Ratings
Table 1. Maximum Tolerated Ratings
Rating
Supply voltage
1
Symbol
V
DDL
(core
voltage)
V
DDH
(I/O voltage)
V
DDSYN
Difference
between V
DDL
to
V
DDSYN
Input voltage
2
Storage temperature range
1
2
This section provides the maximum tolerated voltage and temperature ranges for the MPC852T. Table 1
provides the maximum ratings and operating temperatures.
Value
– 0.3 to 3.4
– 0.3 to 4
– 0.3 to 3.4
100
Unit
V
V
V
mV
V
in
T
stg
GND – 0.3 to V
DDH
– 55 to +150
V
°C
The power supply of the device must start its ramp from 0.0 V.
Functional operating conditions are provided with the DC electrical specifications in Table 5.
Absolute maximum ratings are stress ratings only; functional operation at the maxima is not
guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
Caution:
All inputs that tolerate 5 V cannot be more than 2.5 V greater than V
DDH
. This restriction
applies to power-up and normal operation (that is, if the MPC852T is unpowered, a voltage
greater than 2.5 V must not be applied to its inputs).
Table 2. Operating Temperatures
Rating
Temperature
1
(standard)
Symbol
T
A(min)
T
j(max)
Temperature (extended)
T
A(min)
T
j(max)
1
Value
0
95
– 40
100
Unit
°C
°C
°C
°C
Minimum temperatures are guaranteed as ambient temperature, T
A
. Maximum temperatures are
guaranteed as junction temperature, T
j
.
This device contains circuitry protecting against damage that high-static voltage or electrical fields cause;
however, Motorola recommends taking normal precautions to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or V
DD
). -- V
DDH.
MOTOROLA
MPC852T Hardware Specifications
5
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