ADVANCE
‡
18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH ZBT SRAM
18Mb
ZBT
®
SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High frequency and 100 percent bus utilization
Fast cycle times: 10ns, 11ns and 12ns
Single +3.3V ±5%, or 2.5V ±5% power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
Advanced control logic for minimum control signal
interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os, and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to eliminate
the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or Interleaved Burst Modes
Burst feature (optional)
Pin/function compatibility with 2Mb, 4Mb, and 8Mb
ZBT SRAM
MT55L1MY18F, MT55V1MV18F,
MT55L512Y32F, MT55V512V32F,
MT55L512Y36F, MT55V512V36F
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
2.5V I/O
100-Pin TQFP
1
165-Pin FBGA
OPTIONS
• Timing (Access/Cycle/MHz)
2.5V V
DD
, 2.5V I/O
6.6ns/8.8ns/113 MHz
7.5ns/10ns/100 MHz
9ns/12ns/83 MHz
3.3V V
DD
, 3.3V or 2.5V I/O
7.5ns/10ns/100 MHz
8.5ns/11ns/90 MHz
9ns/12ns/83 MHz
• Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V V
DD
, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
• Packages
100-pin TQFP
165-pin FBGA
119-pin BGA
TQFP MARKING*
-8.8
-10
-12
-10
-11
-12
119-Pin BGA
2
MT55L1MY18F
MT55L512Y32F
MT55L512Y36F
MT55V1MV18F
MT55V512V32F
MT55V512V36F
T
F
B
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-standard MS-028 BHA (PBGA).
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Part Number Example:
None
MT55L512Y32FT-11
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM
MT55L1MY18F_D.p65 – Rev. D, Pub. 9/01
1
©2001, Micron Technology, Inc.
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
‡
PRODUCTS
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH ZBT SRAM
FUNCTIONAL BLOCK DIAGRAM
1 MEG x 18
20
SA0, SA1, SA
MODE
CLK
CKE#
K
CE
ADV/LD#
K
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
20
SA1
D1
SA0
D0
18
Q1 SA1'
SA0'
Q0
20
20
O
U
T
P
U
T
B
U
F
F
E
R
S
E
20
BURST
LOGIC
ADV/LD#
BWa#
BWb#
R/W#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
18
1 Meg x 9 x 2
WRITE
DRIVERS
18
MEMORY
ARRAY
18
S
E
N
S
E
A
M
P
S
D
A
T
A
18
S
T
E
E
R
I
N
G
18
18
DQs
DQPa
DQPb
18
OE#
CE#
CE2
CE2#
INPUT
REGISTER E
READ LOGIC
FUNCTIONAL BLOCK DIAGRAM
512K x 32/36
19
SA0, SA1, SA
MODE
CLK
CKE#
K
CE
ADV/LD#
K
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
19
SA1
D1
SA0
D0
17
Q1 SA1'
SA0'
Q0
19
19
O
U
T
P
U
T
B
U
F
F
E
R
S
E
19
BURST
LOGIC
ADV/LD#
BWa#
BWb#
BWc#
BWd#
R/W#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
36
512K x 8 x 4
(x32)
WRITE
DRIVERS
36
512K x 9 x 4
(x36)
MEMORY
ARRAY
36
S
E
N
S
E
A
M
P
S
D
A
T
A
36
S
T
E
E
R
I
N
G
36
36
DQs
DQPa
DQPb
DQPc
DQPd
36
OE#
CE#
CE2
CE2#
INPUT
E
REGISTER
READ LOGIC
NOTE:
Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams
for detailed information.
18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM
MT55L1MY18F_D.p65 – Rev. D, Pub. 9/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH ZBT SRAM
GENERAL DESCRIPTION
The Micron
®
Zero Bus Turnaround
™
(ZBT
®
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 18Mb ZBT SRAMs integrate a 1 Meg x 18,
512K x 32, or 512K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and a 2-bit burst counter.
These SRAMs are optimized for 100 percent bus utiliza-
tion, eliminating any turnaround cycles for READ to
WRITE, or WRITE to READ, transitions. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single clock input (CLK). The synchro-
nous inputs include all addresses, all data inputs, chip
enable (CE#), two additional chip enables for easy depth
expansion (CE2, CE2#), cycle start input (ADV/LD#), syn-
chronous clock enable (CKE#), byte write enables (BWa#,
BWb#, BWc#, and BWd#), and read/write (R/W#).
Asynchronous inputs include the output enable (OE#,
which may be tied LOW for control signal minimization),
clock (CLK) and snooze enable (ZZ, which may be tied
LOW if unused). There is also a burst mode pin (MODE)
that selects between interleaved and linear burst modes.
MODE may be tied HIGH, LOW or left unconnected if
burst is unused. The flow-through data-out (Q) is en-
abled by OE#. WRITE cycles can be from one to four bytes
wide as controlled by the write control inputs.
All READ, WRITE, and DESELECT cycles are initiated
by the ADV/LD# input. Subsequent burst addresses can
be internally generated as controlled by the burst ad-
vance pin (ADV/LD#). Use of burst mode is optional. It is
allowable to give an address for each individual READ
and WRITE cycle. BURST cycles wrap around after the
fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the flow-through ZBT SRAM uses a LATE WRITE
cycle. For example, if a WRITE cycle begins in clock cycle
one, the address is present on rising edge one. BYTE
WRITEs need to be asserted on the same cycle as the
address. The write data associated with the address is
required one cycle later, or on the rising edge of clock
cycle two.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During a BYTE WRITE cycle, BWa# controls
DQa pins; BWb# controls DQb pins; BWc# controls DQc
pins; and BWd# controls DQd pins. Cycle types can only
be defined when an address is loaded, i.e., when ADV/
LD# is LOW. Parity/ECC bits are only available on the x36
versions.
The device is ideally suited for systems requiring high
bandwidth and zero bus turnaround delays.
Please refer to Micron’s Web site (www.micron.com/
sram)
for the latest data sheet.
DUAL VOLTAGE I/O
The 3.3V V
DD
device is tested for 3.3V and 2.5V I/O
function. The 2.5V V
DD
device is tested for only 2.5V
I/O function.
18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM
MT55L1MY18F_D.p65 – Rev. D, Pub. 9/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH ZBT SRAM
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x18
NC
NC
NC
x32
NF
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
SS
1
V
DD
V
DD
2
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
x36
DQPc
DQc
DQc
PIN # x18
x32
x36
26
V
SS
27
V
DD
Q
28
NC
DQd
DQd
29
NC
DQd
DQd
30
NC
NF
DQPd
31
MODE (LBO#)
32
SA
33
SA
34
SA
35
SA
36
SA1
37
SA0
38
DNU
39
DNU
40
V
SS
41
V
DD
42
DNU
43
DNU
44
SA
45
SA
46
SA
47
SA
48
SA
49
SA
50
SA
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32
NF
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
ZZ
V
DD
V
SS
1
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
x36
DQPa
DQa
DQa
PIN # x18
x32
x36
76
V
SS
77
V
DD
Q
78
NC
DQb
DQb
79
NC
DQb
DQb
80
SA
NF
DQPb
81
SA
82
SA
83
SA
84
SA
85
ADV/LD#
86
OE# (G#)
87
CKE#
88
R/W#
89
CLK
90
V
SS
91
V
DD
92
CE2#
93
BWa#
94
BWb#
95
NC
BWc# BWc#
96
NC
BWd# BWd#
97
CE2
98
CE#
99
SA
100
SA
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
NC
NC
DQa
DQa
DQb
DQb
DQc
DQc
DQb
DQb
DQd
DQd
DQa
DQa
DQb
DQb
DQb
DQb
DQb
NC
DQd
DQd
DQd
DQd
DQa
DQa
DQa
NC
DQb
DQb
DQb
DQb
NOTE:
1. Pins 14 and 66 do not have to be connected directly to V
SS
if the input voltage is
£
V
IL
.
2. Pin 16 does not have to be connected directly to V
DD
if the input voltage is
³
V
IH
.
3. NF for x32 version, DQPx for x36 version.
18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM
MT55L1MY18F_D.p65 – Rev. D, Pub. 9/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH ZBT SRAM
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP
SA
NC
NC
V
DD
Q
V
SS
NC
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
V
SS
2
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NF/DQPb
1
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
V
SS
2
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NF/DQPa
1
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
2
V
DD
V
DD
3
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
NC
V
SS
V
DD
Q
NC
NC
NC
x32/x36
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NOTE:
1. NF for x32 version, DQPx for x36 version.
2. Pins 14 and 66 do not have to be connected directly to V
SS
if the input voltage is
£
V
IL
.
3. Pin 16 does not have to be connected directly to V
DD
if the input voltage is
³
V
IH
.
18Mb: 1 Meg x 18, 512K x 32/36 Flow-Through ZBT SRAM
MT55L1MY18F_D.p65 – Rev. D, Pub. 9/01
NF/DQPc
1
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
SS
2
V
DD
V
DD
3
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NF/DQPd
1
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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