Ordering number : ENN7775
LC82161B-E
Voice Over IP Processor
•
Overview
The LC82161B-E is a special-purpose processor for VoIP
communication equipment such as IP telephones. It
integrates the ARM7TDMI-S
TM
CPU core, an audio signal
processing DSP (FAVOR40), and two 10/100 Base
Ethernet MACs on a single chip.
The LC82161B minimizes audio quality degradation using
a Sanyo-developed jitter buffer control algorithm that runs
on the DSP. Furthermore, this IC's protocol engine
hardware processing reduces the network protocol
processing load on the CPU.
DSP
FAVOR40: 60 MIPS
Audio CODEC: G.711, G.729A
Jitter buffer control
Echo canceller
Melody function
Power saving mode
Ethernet MAC: 2 channels
Protocol engine
Send/receive buffers: 16 KB on-chip buffer memory
A/D and D/A converters: two channels
Package: SQFP208
Supply voltages: I/O: 3.3 V, internal: 2.5 V
•
•
•
•
Features
•
Package Dimensions
unit: mm
3210-SQFP208
[LC82161B]
ARM7 and Peripherals
ARM7TDMI 50MHz
8 KB on-chip cache
16/32-bit bus ROM or flash memory interface
8/16-bit bus external memory interface
Programmable wait states (1 to 16 cycles)
SDRAM controller
32-bit bus, 4-word burst read
DMA controller (2 channels)
Two multifunction timers
8-bit prescaler, 16-bit counter
Watchdog timer
Interrupt controller (23 internal interrupts, 3 external
interrupts)
Two USART interfaces, one SIO interface
27 general-purpose I/O pins
JTAG debugging interface
Power-saving mode
is the registered trademark of ARM Limited.
ARM7TDMI-S is the trademark of ARM Limited.
SANYO: SQFP208
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control
systems, or other applications whose failure can be reasonably expected to result in serious physical and/or
material damage. Consult with your SANYO representative nearest you before using any SANYO products
described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that exceed,
even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters)
listed in products specifications of any and all SANYO products described or contained herein.
33004TN (OT) No.7775-1/19
LC82161B-E
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Maximum supply voltage
I/O voltages
I/O current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
2∗1
V
DD
3∗2
V
I
3, V
O
3
I
I
, I
O
∗3
Pdmax
T
opr
T
stg
Ta
≤
70 °C
Conditions
Ratings
–0.3 to
+3.6
–0.3 to
+4.6
–0.3 to V
DD
3 + 0.3 (Max 4.6 V)
±20
900
–30 to +70
–55 to +125
Unit
V
V
V
mA
mW
°C
°C
Note: *1: Internal and I/O supply voltage
*2: I/O supply voltage
*3: Per individual basic I/O cell.
Allowable Operating Ranges
at Ta =
−30
to
+70 °C
Parameter
Supply voltage
Input voltage
Symbol
V
DD
2
V
DD
3
V
IN
3
Conditions
min
2.3
3.0
0
typ
2.5
3.3
—
max
2.7
3.6
V
DD
3
Unit
V
V
V
DC Characteristics
at Ta =
−30
to
+70 °C,
V
DD
3 = 3.0 V to 3.6 V
Parameter
Input high level voltage
Input low level voltage
Input high level voltage
Input low level voltage
Output high level voltage
Output low level voltage
Output leakage current
Pull-down resistance
Pull-up resistance
Oscillator frequency
Symbol
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
OZ
R
DN
R
UP
f
CLK
1
I
DD
2
Current drain
I
DD
3
I
DDS
2
I
DDS
3
During normal operation (V
DD
2)
During normal operation (V
DD
3)
In power-saving mode (V
DD
2)
In power-saving mode (V
DD
3)
CMOS level pins
CMOS level Schmidt trigger pins
I
OH
= –4 mA
I
OL
= 4 mA
In the high-impedance output state
Conditions
min
0.7 V
DD
3
−
0.75 V
DD
3
−
V
DD
3 - 0.8
—
–10
50
50
—
—
—
—
—
typ
—
—
—
—
—
—
—
100
100
8.192
160
50
10
5
max
—
0.2 V
DD
3
—
0.15 V
DD
3
—
0.4
+10
200
200
—
—
—
—
—
Unit
V
V
V
V
V
V
µA
KΩ
KΩ
MHz
mA
mA
mA
mA
No.7775-2/19
LC82161B-E
Block Diagram
LC82161B-E
TIC
AHB bus
SRAM
Memory
Contoroller
PLL
Cache
Flash
ICE
JTAG
ARM7TDMI
SDRAM
Controller
SDRAM
Program RAM
Data RAM
DMAC
Protocol
Engine
Ethernet
MAC 1
Ethernet
PHY
DSP
FAVOR40
DPRAM
Ethernet
MAC 2
Ethernet
PHY
MIC/
Speaker
Amp
A/D,D/A
Bus bridge
IRQ
Controller
USART1
LCD
Timer
USART2
KEY,LED
GPIO
SIO
APB bus
No.7775-3/19
LC82161B-E
Pin Functions
I/O
I
O
B
P
NC
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Input pins
Output pins
Bidirectional pins
Power supply pins
Unused pins
Pin name
DGND
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
TEST3
TEST2
TEST1
PVDD2
PGND
RIN1
PLLI1
PLLO1
TEST0
ROMBUSW
A4
A3
A2
A1
A0
MWRLn
MWRHn
MRDn
RESETn
XTAL1
XTAL2
DVDD3
DGND
CS0n
CS1n/PD4
CS2n/PD5
CS3n/PD6
DRCS1n
DRCS0n
RASn
CASn
DRCLK
DRWE
DQM1
DQM0
M1_TXEN
3IC
3IS
3ICD
3ICU
3O4
I/O
P
O
O
O
O
O
O
O
O
O
O
O
I
I
I
P
P
I
I
O
I
I
O
O
O
O
O
O
O
O
I
I
O
P
P
O
B
B
B
O
O
O
O
O
O
O
O
O
3O4
3ICU/3T4
3ICU/3T4
3ICU/3T4
3O4
3O4
3O4
3O4
3O8
3O4
3O4
3O4
3O4
2A
2A
2A
3ICD
3ICD
3O4
3O4
3O4
3O4
3O4
3O4
3O4
3O4
3IS
X
X
Digital system power supply (+3.3 V)
Digital system ground
External memory chip select 0
External memory chip select 1 or I/O port
External memory chip select 2 or I/O port
External memory chip select 3 or I/O port
SDRAM chip select 1
SDRAM chip select 0
Row address strobe
Column address strobe
SDRAM clock
SDRAM write enable
SDRAM byte mask 1
SDRAM byte mask 0
MAC1 transmit enable
External memory write signal
External memory write signal
External memory read signal
Reset
Crystal oscillator connection (8.192 MHz)
Address bus
3O4
3O4
3O4
3O4
3O4
3O4
3O4
3O4
3O4
3O4
3O4
3ICD
3ICD
3ICD
Test
Test
Test
PLL power supply (+2.5 V)
PLL ground
PLL1 bias input
PLL1 VCO input
PLL1 charge pump output
Test
Memory bus width selection
Address bus
3.3 V CMOS inputs
3.3 V Schmidt trigger inputs
3.3 V CMOS inputs with pull-down resistor
3.3 V CMOS inputs with pull-up resistor
3.3 V 4 mA outputs
Pin type
Digital system ground
Pin type
3O8
3T4
3A
2A
X
3.3 V 8 mA output
3.3 V 4 mA tristate output
3.3 V analog
2.5 V analog
Oscillator amplifier
Function
Continued on next page.
No.7775-4/19
LC82161B-E
Continued from preceding page.
Pin No.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
Pin name
M1_TXCLK
M1_TXD3
M1_TXD2
DVDD2
DGND
M1_TXD1
M1_TXD0
M1_RXCLK
M1_RXDV
M1_RXER
M1_RXD3
M1_RXD2
M1_RXD1
M1_RXD0
M1_CRS
M1_COL
M1_MDC
M1_MDIO
M2_TXEN
DVDD3
DGND
M2_TXCLK
M2_TXD3
M2_TXD2
M2_TXD1
M2_TXD0
M2_RXCLK
M2_RXDV
M2_RXER
M2_RXD3
M2_RXD2
M2_RXD1
M2_RXD0
M2_CRS
M2_COL
M2_MDC
M2_MDIO
DVDD2
DGND
BIGEND
DIVCK/PB11
PB10
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA15
PA14
PA13
I/O
I
O
O
P
P
O
O
I
I
I
I
I
I
I
I
I
O
B
O
P
P
I
O
O
O
O
I
I
I
I
I
I
I
I
I
O
B
P
P
I
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
3ICD
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
3IC/3T4
I/O ports
3IC
3O4
3O4
3O4
3O4
3IC
3IC
3IC
3IC
3IC
3IC
3IC
3IC
3IC
3O4
3IC/3T4
3O4
3O4
3IC
3IC
3IC
3IC
3IC
3IC
3IC
3IC
3IC
3O4
3IC/3T4
3O4
Pin type
3IC
3O4
3O4
MAC1 transmit clock
MAC1 transmit data
MAC1 transmit data
Digital system power supply (+2.5 V)
Digital system ground
MAC1 transmit data
MAC1 transmit data
MAC1 receive clock
MAC1 receive data valid
MAC1 receive data error
MAC1 receive data
MAC1 receive data
MAC1 receive data
MAC1 receive data
MAC1 carrier sense
MAC1 collision detection
MAC1 MII control clock
MAC1 MII control data
MAC2 transmit enable
Digital system power supply (+3.3 V)
Digital system ground
MAC2 transmit clock
MAC2 transmit data
MAC2 transmit data
MAC2 transmit data
MAC2 transmit data
MAC2 receive clock
MAC2 receive data valid
MAC2 receive data error
MAC2 receive data
MAC2 receive data
MAC2 receive data
MAC2 receive data
MAC2 carrier sense
MAC2 collision detection
MAC2 MII control clock
MAC2 MII control data
Digital system power supply (+2.5 V)
Digital system ground
Endian selection
Divided clock output or I/O port
Function
Continued on next page.
No.7775-5/19
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