PJSDA05C-4
TVS ARRAY QUAD FOR ESD PROTECTION
This Penta TVS Array has been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up
events in CMOS circuitry operating at 5Vdc and below. This TVS array offers an integrated solution to protect up
to 4 data lines where the board space is a premium.
FEATURES
•
•
•
•
•
80W power dissipation (8/20μs waveform)
Low leakage current,maximum of 1μA@5Vdc
Very low clamping voltage
IEC61000-4-2 ESD 15kV air, 8kV Contact Compliance
In compliance with EU RoHS 2002/95/EC directives
12 30
1
2
3
Fig.126
MAXIMUM RATINGS
Parameter
P e a k P uls e P o we r ( 8 /2 0
μ
s Wa ve f o rm)
P e a k P uls e C ur re nt ( 8 /2 0
μ
s Wa ve fo r m)
E S D Vo lt a g e (HB M )
O p e r a ti ng Te m p e ra t ure Ra ng e
S t o ra g e Te m p e ra t ur e Ra ng e
Symbol
P
PP
I
PP
Value
80
5.0
>25
-55 to + 150
-55 to + 150
MAX.
035 0.9
• Case: SOT23-6L molded plastic
• Terminals:Solder plated, solderable per MIL-STD-750,Method 2026
• Weight: 0.0005 ounce, 0.0141 gram
5
6
• Marking : QCG
4
119
MECHANICAL DATA
Units
W
A
kV
o
V
ESD
T
J
T
S TG
C
C
o
ELECTRICAL CHARACTERISTICS T
J
=25
o
C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20μs)
Clamping Voltage (8/20μs)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
C
J
C
J
I
BR
=1mA
V
R
=5V
I
PP
=1A
I
PP
=4A
0Vdc Bias f=1MHz Between I/O pins and pin 2
5Vdc Bias f=1MHz Between I/O pins and pin 2
Conditions
-
Min.
-
6.2
-
-
-
-
-
Typ.
-
-
-
-
-
15
7
Max.
5.0
8.0
1
12
15
17
10
Units
V
V
μA
V
V
pF
pF
April 30.2010-REV.00
PAGE . 1
PJSDA05C-4
100
90
80
25
50% of I pp@20
m
s
C
J
, Junction Capacitance (pF)
20
15
10
5
0
0
1
2
3
4
5
Pe rce nt of I pp
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
Rise time 10-90%-8
m
s
time,
m
s
FIG 1-PULSE WAVEFORM
V
R
, Reverse Bias Voltage (V)
FIG 2- TYPICAL JUNCTION CAPACITANCE UNDER BIAS
IPP, Peak Current (A) ,8/20
m
sec
100
6
5
4
3
2
1
0
8
9
10
11
12
I
R
, Reverse Leakage
Current (nA)
10
1
0
20
40
60
80
100
120
o
140
160
T
J
, Junction Temperature ( C)
VC , Clamping Voltage(V)
FIG 3- TYPICAL LEAKAGE CURRENT
vs JUNCTION TEMPERATURE
FIG 4- CLAMPING VOLTAGE vs PEAK CURRENT
April 30.2010-REV.00
PAGE . 2
PJSDA05C-4
MOUNTING PAD LAYOUT
ORDER INFORMATION
• Packing information
T/R - 10K per 13" plastic Reel
T/R - 3K per 7” plastic Reel
LEGAL STATEMENT
Copyright PanJit International, Inc 2010
The information presented in this document is believed to be accurate and reliable. The specifications and information herein
are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit
does not convey any license under its patent rights or rights of others.
April 30.2010-REV.00
PAGE .
3
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