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MT29C8G96MAZBADJV-5IT

产品描述Memory Circuit, 512MX16, CMOS, PBGA168, VFBGA-168
产品类别存储    存储   
文件大小4MB,共220页
制造商Micron Technology
官网地址http://www.mdtic.com.tw/
标准
下载文档 详细参数 全文预览

MT29C8G96MAZBADJV-5IT概述

Memory Circuit, 512MX16, CMOS, PBGA168, VFBGA-168

MT29C8G96MAZBADJV-5IT规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Micron Technology
包装说明VFBGA-168
Reach Compliance Codecompliant
其他特性MOBILE LPDDR DEVICE ALSO AVAILABLE
JESD-30 代码S-PBGA-B168
长度12 mm
内存密度8589934592 bit
内存集成电路类型MEMORY CIRCUIT
内存宽度16
功能数量1
端子数量168
字数536870912 words
字数代码512000000
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织512MX16
封装主体材料PLASTIC/EPOXY
封装代码VFBGA
封装形状SQUARE
封装形式GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度)NOT SPECIFIED
座面最大高度1 mm
最大供电电压 (Vsup)1.95 V
最小供电电压 (Vsup)1.7 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式BALL
端子节距0.5 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度12 mm

MT29C8G96MAZBADJV-5IT文档预览

Micron Confidential and Proprietary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Features
NAND Flash and Mobile LPDDR
168-Ball Package-on-Package (PoP) MCP
Combination Memory (TI OMAP™)
MT29C4G48MAYBAAKQ-5 WT, MT29C4G48MAZBAAKQ-5 WT,
MT29C4G96MAYBACJG-5 WT, MT29C4G96MAZBACJG-5 WT,
MT29C8G96MAYBADJV-5 WT, MT29C8G96MAZBADJV-5 WT
MT29C4G48MAZBAAKQ-5 IT, MT29C4G96MAZBACJG-5 IT
MT29C8G96MAZBADJV-5 IT
Features
Micron
®
NAND Flash and LPDDR components
RoHS-compliant, “green” package
Separate NAND Flash and LPDDR interfaces
Space-saving multichip package/package-on-package
combination
• Low-voltage operation (1.70–1.95V)
• Wireless temperature range: –25°C to +85°C
• Industrial temperature range: –40°C to +85°C
Figure 1: PoP Block Diagram
NAND Flash
Power
NAND Flash
Device
NAND Flash
Interface
NAND Flash-Specific Features
Organization
• Page size
– x8: 2112 bytes (2048 + 64 bytes)
– x16: 1056 words (1024 + 32 words)
• Block size: 64 pages (128K + 4K bytes)
LPDRAM Power
LPDRAM
Device
LPDRAM
Interface
Mobile LPDDR-Specific Features
No external voltage reference required
No minimum clock rate requirement
1.8V LVCMOS-compatible inputs
Programmable burst lengths
Partial-array self refresh (PASR)
Deep power-down (DPD) mode
Selectable output drive strength
STATUS REGISTER READ (SRR) supported
1
Notes:
1. Contact factory for remapped SRR output.
2. For physical part markings, see page 2.
PDF: 09005aef846d1f3b
168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. D 4/13
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Features
Part Numbering Information
Micron NAND Flash and LPDRAM devices are available in different configurations and densities. The MCP/PoP
part numbering guide is available at
www.micron.com/numbering.
Figure 2: Part Number Chart
MT 29C XX XXX X
Micron Technology
Product Family
NAND Flash Density
LPDRAM Density
Operating Voltage Range
NAND Flash Configuration
X
X
X
XX -X
XX XX
Production Status
Operating Temperature Range
LPDRAM Access Time
Package Codes
Chip Count
LPDRAM Configuration
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead,
an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are
cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site:
www.micron.com/decoder.
To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/
Label,” at
www.micron.com/csn.
PDF: 09005aef846d1f3b
168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. D 4/13
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Features
Contents
MCP General Description ...............................................................................................................................
Ball Assignments and Descriptions .................................................................................................................
Electrical Specifications ..................................................................................................................................
Device Diagrams ............................................................................................................................................
Package Dimensions .......................................................................................................................................
4Gb, 8Gb: x8, x16 NAND Flash Memory ...........................................................................................................
Features .....................................................................................................................................................
General Description .......................................................................................................................................
Architecture ...................................................................................................................................................
Device and Array Organization ........................................................................................................................
Asynchronous Interface Bus Operation ...........................................................................................................
Asynchronous Enable/Standby ...................................................................................................................
Asynchronous Commands ..........................................................................................................................
Asynchronous Addresses ............................................................................................................................
Asynchronous Data Input ...........................................................................................................................
Asynchronous Data Output .........................................................................................................................
Write Protect# ............................................................................................................................................
Ready/Busy# ..............................................................................................................................................
Device Initialization .......................................................................................................................................
Command Definitions ....................................................................................................................................
Reset Operations ............................................................................................................................................
RESET (FFh) ...............................................................................................................................................
Identification Operations ................................................................................................................................
READ ID (90h) ............................................................................................................................................
READ ID Parameter Tables ..............................................................................................................................
READ PARAMETER PAGE (ECh) ......................................................................................................................
Bare Die Parameter Page Data Structure Tables ................................................................................................
READ UNIQUE ID (EDh) ................................................................................................................................
Feature Operations .........................................................................................................................................
SET FEATURES (EFh) ..................................................................................................................................
GET FEATURES (EEh) .................................................................................................................................
Status Operations ...........................................................................................................................................
READ STATUS (70h) ...................................................................................................................................
READ STATUS ENHANCED (78h) ................................................................................................................
Column Address Operations ...........................................................................................................................
RANDOM DATA READ (05h-E0h) ................................................................................................................
RANDOM DATA READ TWO-PLANE (06h-E0h) ............................................................................................
RANDOM DATA INPUT (85h) ......................................................................................................................
PROGRAM FOR INTERNAL DATA INPUT (85h) ...........................................................................................
Read Operations .............................................................................................................................................
READ MODE (00h) .....................................................................................................................................
READ PAGE (00h-30h) ................................................................................................................................
READ PAGE CACHE SEQUENTIAL (31h) ......................................................................................................
READ PAGE CACHE RANDOM (00h-31h) ....................................................................................................
READ PAGE CACHE LAST (3Fh) ..................................................................................................................
READ PAGE TWO-PLANE 00h-00h-30h .......................................................................................................
Program Operations .......................................................................................................................................
PROGRAM PAGE (80h-10h) .........................................................................................................................
PROGRAM PAGE CACHE (80h-15h) .............................................................................................................
PROGRAM PAGE TWO-PLANE (80h-11h) ....................................................................................................
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PDF: 09005aef846d1f3b
168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. D 4/13
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Features
Erase Operations ............................................................................................................................................ 81
ERASE BLOCK (60h-D0h) ............................................................................................................................ 81
ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 82
Internal Data Move Operations ....................................................................................................................... 83
READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 84
PROGRAM FOR INTERNAL DATA MOVE (85h–10h) ..................................................................................... 85
PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................. 86
Block Lock Feature ......................................................................................................................................... 87
WP# and Block Lock ................................................................................................................................... 87
UNLOCK (23h-24h) .................................................................................................................................... 87
LOCK (2Ah) ................................................................................................................................................ 90
LOCK TIGHT (2Ch) ..................................................................................................................................... 91
BLOCK LOCK READ STATUS (7Ah) .............................................................................................................. 92
One-Time Programmable (OTP) Operations .................................................................................................... 94
Legacy OTP Commands .............................................................................................................................. 94
OTP DATA PROGRAM (80h-10h) ................................................................................................................. 95
RANDOM DATA INPUT (85h) ...................................................................................................................... 96
OTP DATA PROTECT (80h-10) ..................................................................................................................... 97
OTP DATA READ (00h-30h) ......................................................................................................................... 99
Two-Plane Operations ................................................................................................................................... 101
Two-Plane Addressing ............................................................................................................................... 101
Interleaved Die (Multi-LUN) Operations ......................................................................................................... 110
Error Management ........................................................................................................................................ 111
Internal ECC and Spare Area Mapping for ECC ............................................................................................... 113
Electrical Specifications ................................................................................................................................. 115
Electrical Specifications – DC Characteristics and Operating Conditions .......................................................... 117
Electrical Specifications – AC Characteristics and Operating Conditions .......................................................... 119
Electrical Specifications – Program/Erase Characteristics ................................................................................ 122
Asynchronous Interface Timing Diagrams ...................................................................................................... 123
2Gb: x16, x32 Mobile LPDDR SDRAM ............................................................................................................. 135
Features .................................................................................................................................................... 135
General Description .................................................................................................................................. 137
Functional Block Diagrams ............................................................................................................................ 138
Electrical Specifications ................................................................................................................................. 140
Electrical Specifications – I
DD
Parameters ....................................................................................................... 143
Electrical Specifications – AC Operating Conditions ........................................................................................ 149
Output Drive Characteristics .......................................................................................................................... 154
Functional Description .................................................................................................................................. 157
Commands ................................................................................................................................................... 158
DESELECT ................................................................................................................................................ 159
NO OPERATION ........................................................................................................................................ 159
LOAD MODE REGISTER ............................................................................................................................ 159
ACTIVE ..................................................................................................................................................... 159
READ ........................................................................................................................................................ 160
WRITE ...................................................................................................................................................... 161
PRECHARGE ............................................................................................................................................. 162
BURST TERMINATE .................................................................................................................................. 163
AUTO REFRESH ........................................................................................................................................ 163
SELF REFRESH .......................................................................................................................................... 164
DEEP POWER-DOWN ................................................................................................................................ 164
Truth Tables .................................................................................................................................................. 165
State Diagram ............................................................................................................................................... 170
PDF: 09005aef846d1f3b
168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. D 4/13
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Features
Initialization ................................................................................................................................................. 171
Standard Mode Register ................................................................................................................................. 174
Burst Length ............................................................................................................................................. 175
Burst Type ................................................................................................................................................. 175
CAS Latency .............................................................................................................................................. 176
Operating Mode ........................................................................................................................................ 177
Extended Mode Register ................................................................................................................................ 178
Temperature-Compensated Self Refresh ..................................................................................................... 178
Partial-Array Self Refresh ........................................................................................................................... 179
Output Drive Strength ............................................................................................................................... 179
Status Read Register ...................................................................................................................................... 180
Bank/Row Activation ..................................................................................................................................... 182
READ Operation ............................................................................................................................................ 183
WRITE Operation .......................................................................................................................................... 194
PRECHARGE Operation ................................................................................................................................. 206
Auto Precharge .............................................................................................................................................. 206
Concurrent Auto Precharge ........................................................................................................................ 207
AUTO REFRESH Operation ............................................................................................................................ 213
SELF REFRESH Operation .............................................................................................................................. 214
Power-Down ................................................................................................................................................. 215
Deep Power-Down .................................................................................................................................... 217
Clock Change Frequency ............................................................................................................................... 219
Revision History ............................................................................................................................................ 220
Rev. D – 4/13 ............................................................................................................................................. 220
Rev. C – 12/12 ............................................................................................................................................ 220
Rev. B – 10/12 ............................................................................................................................................ 220
Rev. A – 05/11 ............................................................................................................................................ 220
PDF: 09005aef846d1f3b
168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. D 4/13
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
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