Micron Confidential and Proprietary
Preliminary
‡
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Features
NAND Flash and Mobile LPDDR
168-Ball Package-on-Package (PoP) MCP
Combination Memory (TI OMAP™)
MT29C4G48MAYAPAKQ-5 IT, MT29C4G48MAZAPAKQ-5 IT,
MT29C4G48MAZAPAKQ-6 IT, MT29C4G96MAZAPCJG-5 IT,
MT29C4G96MAZAPCJG-6 IT, MT29C8G96MAZAPDJV-5 IT,
MT29C8G96MAZAPDJV-6 IT
Features
Micron
®
NAND Flash and LPDDR components
RoHS-compliant, “green” package
Separate NAND Flash and LPDDR interfaces
Space-saving multichip package/package-on-package
combination
•
Low-voltage operation (1.70–1.95V)
•
Industrial temperature range: –40°C to +85°C
•
•
•
•
Figure 1: PoP Block Diagram
NAND Flash
Power
NAND Flash
Device
NAND Flash
Interface
NAND Flash-Specific Features
Organization
•
Page size
–
x8: 2112 bytes (2048 + 64 bytes)
–
x16: 1056 words (1024 + 32 words)
•
Block size: 64 pages (128K + 4K bytes)
LPDRAM Power
LPDRAM
Device
LPDRAM
Interface
Mobile LPDDR-Specific Features
•
•
•
•
•
•
•
•
No external voltage reference required
No minimum clock rate requirement
1.8V LVCMOS-compatible inputs
Programmable burst lengths
Partial-array self refresh (PASR)
Deep power-down (DPD) mode
Selectable output drive strength
STATUS REGISTER READ (SRR) supported
1
Notes:
1. Contact factory for remapped SRR output.
2. For physical part markings, see Part Number-
ing Information (page 2).
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. G 06/10
1
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Features
Part Numbering Information
Micron NAND Flash and LPDRAM devices are available in different configurations and densities. The MCP/PoP
part numbering guide is available at
www.micron.com/numbering.
Figure 2: Part Number Chart
MT 29C XX XXX X
Micron Technology
Product Family
NAND Flash Density
LPDRAM Density
Operating Voltage Range
NAND Flash Configuration
X
X
X
X
X
X
XX
Production Status
Operating Temperature Range
LPDRAM Access Time
Package Codes
Chip Count
LPDRAM Configuration
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead,
an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are
cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site:
www.micron.com/decoder.
To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/
Label,” at
www.micron.com/csn.
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. G 06/10
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Contents
MCP General Description ...............................................................................................................................
Ball Assignments and Descriptions .................................................................................................................
Electrical Specifications ..................................................................................................................................
Device Diagrams ............................................................................................................................................
Package Dimensions ......................................................................................................................................
4Gb, 8Gb: x8, x16 NAND Flash Memory ...........................................................................................................
Features .....................................................................................................................................................
General Description ...................................................................................................................................
Architecture ...................................................................................................................................................
Device and Array Organization .......................................................................................................................
Asynchronous Interface Bus Operation ...........................................................................................................
Asynchronous Enable/Standby ...................................................................................................................
Asynchronous Commands ..........................................................................................................................
Asynchronous Addresses ............................................................................................................................
Asynchronous Data Input ...........................................................................................................................
Asynchronous Data Output ........................................................................................................................
Write Protect# ............................................................................................................................................
Ready/Busy# ..............................................................................................................................................
Device Initialization .......................................................................................................................................
Command Definitions ....................................................................................................................................
Reset Operations ............................................................................................................................................
RESET (FFh) ...............................................................................................................................................
Identification Operations ................................................................................................................................
READ ID (90h) ............................................................................................................................................
READ ID Parameter Tables .............................................................................................................................
READ PARAMETER PAGE (ECh) ......................................................................................................................
Bare Die Parameter Page Data Structure Tables ..............................................................................................
READ UNIQUE ID (EDh) ................................................................................................................................
Feature Operations .........................................................................................................................................
SET FEATURES (EFh) .................................................................................................................................
GET FEATURES (EEh) .................................................................................................................................
Status Operations ...........................................................................................................................................
READ STATUS (70h) ...................................................................................................................................
READ STATUS ENHANCED (78h) ...............................................................................................................
Column Address Operations ...........................................................................................................................
RANDOM DATA READ (05h-E0h) ................................................................................................................
RANDOM DATA READ TWO-PLANE (06h-E0h) ...........................................................................................
RANDOM DATA INPUT (85h) .....................................................................................................................
PROGRAM FOR INTERNAL DATA INPUT (85h) ...........................................................................................
Read Operations .............................................................................................................................................
READ MODE (00h) .....................................................................................................................................
READ PAGE (00h-30h) ................................................................................................................................
READ PAGE CACHE SEQUENTIAL (31h) .....................................................................................................
READ PAGE CACHE RANDOM (00h-31h) ....................................................................................................
READ PAGE CACHE LAST (3Fh) ..................................................................................................................
READ PAGE TWO-PLANE 00h-00h-30h .......................................................................................................
Program Operations .......................................................................................................................................
PROGRAM PAGE (80h-10h) ........................................................................................................................
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................
PROGRAM PAGE TWO-PLANE (80h-11h) ....................................................................................................
11
12
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25
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32
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PDF: 09005aef83ba4387
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3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Erase Operations ............................................................................................................................................ 80
ERASE BLOCK (60h-D0h) ............................................................................................................................ 80
ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 81
Internal Data Move Operations ....................................................................................................................... 82
READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................ 83
PROGRAM FOR INTERNAL DATA MOVE (85h–10h) .................................................................................... 84
PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................ 85
Block Lock Feature ......................................................................................................................................... 86
WP# and Block Lock ................................................................................................................................... 86
UNLOCK (23h-24h) .................................................................................................................................... 86
LOCK (2Ah) ................................................................................................................................................ 89
LOCK TIGHT (2Ch) ..................................................................................................................................... 90
BLOCK LOCK READ STATUS (7Ah) ............................................................................................................. 91
One-Time Programmable (OTP) Operations .................................................................................................... 93
Legacy OTP Commands .............................................................................................................................. 93
OTP DATA PROGRAM (80h-10h) ................................................................................................................. 94
RANDOM DATA INPUT (85h) .................................................................................................................... 95
OTP DATA PROTECT (80h-10) .................................................................................................................... 96
OTP DATA READ (00h-30h) ........................................................................................................................ 98
Two-Plane Operations ................................................................................................................................... 100
Two-Plane Addressing ............................................................................................................................... 100
Interleaved Die (Multi-LUN) Operations ........................................................................................................ 109
Error Management ........................................................................................................................................ 110
Internal ECC and Spare Area Mapping for ECC ............................................................................................... 112
Electrical Specifications ................................................................................................................................. 114
Electrical Specifications – DC Characteristics and Operating Conditions ......................................................... 116
Electrical Specifications – AC Characteristics and Operating Conditions .......................................................... 118
Electrical Specifications – Program/Erase Characteristics ................................................................................ 121
Asynchronous Interface Timing Diagrams ...................................................................................................... 122
2Gb: x16, x32 Mobile LPDDR SDRAM ............................................................................................................. 134
Features .................................................................................................................................................... 134
General Description .................................................................................................................................. 135
Functional Block Diagrams ............................................................................................................................ 136
Electrical Specifications ................................................................................................................................. 138
Electrical Specifications – I
DD
Parameters ....................................................................................................... 141
Electrical Specifications – AC Operating Conditions ........................................................................................ 147
Output Drive Characteristics .......................................................................................................................... 152
Functional Description .................................................................................................................................. 155
Commands ................................................................................................................................................... 156
DESELECT ............................................................................................................................................... 157
NO OPERATION ....................................................................................................................................... 157
LOAD MODE REGISTER ........................................................................................................................... 157
ACTIVE .................................................................................................................................................... 157
READ ....................................................................................................................................................... 158
WRITE ..................................................................................................................................................... 159
PRECHARGE ............................................................................................................................................ 160
BURST TERMINATE ................................................................................................................................. 161
AUTO REFRESH ....................................................................................................................................... 161
SELF REFRESH .......................................................................................................................................... 162
DEEP POWER-DOWN ............................................................................................................................... 162
Truth Tables .................................................................................................................................................. 163
State Diagram ............................................................................................................................................... 168
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. G 06/10
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Initialization ................................................................................................................................................. 169
Standard Mode Register ................................................................................................................................. 172
Burst Length ............................................................................................................................................. 172
Burst Type ................................................................................................................................................ 173
CAS Latency ............................................................................................................................................. 174
Operating Mode ........................................................................................................................................ 175
Extended Mode Register ................................................................................................................................ 176
Temperature-Compensated Self Refresh ................................................................................................... 176
Partial-Array Self Refresh .......................................................................................................................... 177
Output Drive Strength ............................................................................................................................... 177
Status Read Register ...................................................................................................................................... 178
Bank/Row Activation ..................................................................................................................................... 180
READ Operation ............................................................................................................................................ 181
WRITE Operation .......................................................................................................................................... 192
PRECHARGE Operation ................................................................................................................................. 204
Auto Precharge .............................................................................................................................................. 204
Concurrent Auto Precharge ....................................................................................................................... 205
AUTO REFRESH Operation ............................................................................................................................ 210
SELF REFRESH Operation ............................................................................................................................. 211
Power-Down ................................................................................................................................................. 212
Deep Power-Down ................................................................................................................................... 214
Clock Change Frequency ............................................................................................................................... 216
Revision History ............................................................................................................................................ 217
Rev. G, Preliminary – 6/10 .......................................................................................................................... 217
Rev. F, Preliminary – 03/10 ........................................................................................................................ 217
Rev. E, Preliminary – 02/10 ........................................................................................................................ 217
Rev. D, Preliminary – 01/10 ........................................................................................................................ 217
Rev. C, Preliminary – 12/09 ........................................................................................................................ 217
Rev. B, Preliminary – 10/09 ........................................................................................................................ 217
Rev. A, Preliminary – 7/09 .......................................................................................................................... 218
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. G 06/10
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
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