June 2008
HYS64T128020EMV–2.5C2
H Y S 64 T 128 020E M V– 3 S– C 2
2 1 4 - P i n 1 . 5 V U n b u f f e r e d D D R 2 S D R A M Mi c r o D I M M
Modules
MDIMM SDRAM
EU RoHS Compliant
Internet Data Sheet
Rev. 1.00
Internet Data Sheet
HYS64T128020EMV–[2.5/3S](–)C2
Unbuffered DDR2 SDRAM MicroDIMM Modules
HYS64T128020EMV–2.5C2, HYS64T128020EMV–3S–C2
Revision History: 2008-06, Rev. 1.00
Page
All
All
Subjects (major changes since last revision)
Final data sheet and adapted to internet edition.
New Document
Previous Revision: 2008-01, Rev. 0.50
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qag_techdoc_A4, 4.20, 2008-01-25
01242008-CDK4-KSK6
2
Internet Data Sheet
HYS64T128020EMV–[2.5/3S](–)C2
Unbuffered DDR2 SDRAM MicroDIMM Modules
1
Overview
This chapter gives an overview of the 214-pin Micro-DIMM DDR2 SDRAM modules product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Auto Refresh for temperatures above 85 °C
t
REFI
= 3.9
μs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.5 and SSTL_1.8
compatible.
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT).
2-piece type Mezzanine Socket with 0,4 mm contact
centers.
Serial Presence Detect with E
2
PROM.
MDIMM Dimensions (nominal): 30 mm high, 54 mm wide
Based on standard reference layouts Raw Cards 'A'.
RoHS compliant products
1)
.
• 214-Pin PC2-6400 and PC2-5300 DDR2 SDRAM memory
modules.
• Two rank 128M
×
64 module organization, and 64M
×
16
chip organization.
• 1GB Modules built with 1 Gbit DDR2 SDRAMs in chipsize
packages PG-TFBGA-84.
• Power Supply
V
DD.MIN
=
V
DDQ.MIN
=1.45 V
V
DD.NOMINAL
=
V
DDQ.NOMINAL
=1.50 V
V
DD.MAX
=
V
DDQ.MAX
=1.9 V
• All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Programmable CAS Latencies (3, 4, 5, 6 and 7), Burst
Length (8 & 4).
• Auto Refresh (CBR) and Self Refresh.
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
CL3
CL4
CL5
CL6
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
DDR2
PC2
–2.5
–800E
–6400E
6–6–6
–3S
–667D
–5300D
5–5–5
200
266
333
–
15
15
45
Unit
Note
t
CK
MHz
MHz
MHz
MHz
ns
ns
ns
f
CK3
f
CK4
f
CK5
f
CK6
t
RCD
t
RP
t
RAS
200
266
333
400
15
15
45
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products
.
Rev. 1.00, 2008-06
01242008-CDK4-KSK6
3
Internet Data Sheet
HYS64T128020EMV–[2.5/3S](–)C2
Unbuffered DDR2 SDRAM MicroDIMM Modules
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Min. Row Cycle Time
DDR2
PC2
–2.5
–800E
–6400E
6–6–6
–3S
–667D
–5300D
5–5–5
60
Unit
Note
t
CK
ns
1)2)
Precharge-All (8 banks) command period
17.5
18
ns
1) This
t
PREA
value is the minimum value at which this chip will be functional.
2) Precharge-All command for an 8 bank device will equal to
t
RP
+ 1 ×
t
CK
or
t
nRP
+ 1 × nCK, depending on the speed bin,
where
t
nRP
= RU{
t
RP
/
t
CK(avg)
} and
t
RP
is the value for a single bank precharge.
t
RC
t
PREA
60
1.2
Description
The memory array is designed with 1 Gbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
2
PROM
device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The Qimonda HYS64T128020EMV–[2.5/3S](–)C2 module
family are Micro-DIMM modules “MDIMMs” with 30 mm
height based on DDR2 technology. DIMMs are available as
non-ECC modules in128M
×
64 (1GB) in organization and
density, intended for mounting into 214-pin connector
sockets.
TABLE 2
Ordering Information
Product Type
1)
PC2-6400 (6-6-6)
HYS64T128020EMV-2.5C2
PC2-5300 (5-5-5)
HYS64T128020EMV-3S-C2
1GB 2R×16 PC2–5300M–555–12–A0
2 Ranks, Non-ECC
1Gbit (×16)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400M–666–12–A0" where
6400M means Micro-DIMM modules with 6.40 GB/sec Module Bandwidth and "666–12" means Column Address Strobe (CAS) latency
=6, Row Column Delay (RCD) latency = 6 and Row Precharge (RP) latency = 6 using the Industry Standard SPD Revision 1.2 and
produced on the Raw Card "A".
Compliance Code
2)
Description
SDRAM Technology
1GB 2R×16 PC2–6400M–666–12–A0
2 Ranks, Non-ECC
1Gbit (×16)
TABLE 3
Address Format
DIMM
Density
1GB
Module
Organization
128M
×
64
Memory
Ranks
2
ECC/
Non-ECC
Non-ECC
# of SDRAMs # of row/bank/column
bits
8
13/3/10
Raw
Card
A
Rev. 1.00, 2008-06
01242008-CDK4-KSK6
4
Internet Data Sheet
HYS64T128020EMV–[2.5/3S](–)C2
Unbuffered DDR2 SDRAM MicroDIMM Modules
TABLE 4
Components on Modules
Product Type
1)2)
HYS64T128020EMV
DRAM Components
1)
HYB15T1G160C2F
DRAM Density
1Gbit
DRAM Organisation
64M
×
16
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.00, 2008-06
01242008-CDK4-KSK6
5
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