INTEGRATED CIRCUITS
SA57026
300 mA LDO with ON/OFF control and
independent delayed RESET function
Product data
File under Integrated Circuits, Standard Analog
2001 Oct 03
Philips
Semiconductors
Philips Semiconductors
Product data
300 mA LDO with ON/OFF control and
independent delayed RESET function
SA57026
GENERAL DESCRIPTION
The SA57026 has an extremely precise fixed output with a typical
accuracy of
±2%.
It is designed to provide very low dropout and low
noise in CD-ROM drives, battery-operated systems, and portable
computers applications. This regulator consists of an internal
voltage reference, an error amplifier, a driver with current limiter, and
a thermal shut-down mechanism.
An Active-LOW RESET is assered when the detected voltage
(V
DET
) falls below the reset voltage threshold. The RESET output
remains low for 30
µs
(typical) when zero capacitance connected to
Cd pin. The reset time delay can be adjusted by replacing
cpacitance values from Cd pin to Ground.
The device is available in the SOP-7B package.
FEATURES
•
Very low dropout voltage: 500 mV typ. (I
out
= 50 mA)
•
High precision output voltage:
±2%
•
Output current capacity: 300 mA
•
Low noise: 40 mV
rms
typ. @ 20 Hz to 80 KHz and for C
n
= 10 nF
•
Extremely good line regulation: 10 mV typical
•
Extremely good load regulation: 20 mV typical
•
Low temperature drift co-efficient to V
out
:
±100
ppm/°C
•
Internal current limit and thermal shut-down circuits
•
Adjustment-free reset detection voltage: 4.2 V typ.
•
Delay time can be adjusted by external capacitor
•
Wide operating temperature range: –40
°C
to +85
°C
BLOCK DIAGRAM
APPLICATIONS
•
CD-ROM drives
•
Electronic notebooks, PDAs and palmtop computers
•
Cameras, VCRs and camcorders
•
PCMCIA cards
•
Modems
•
Battery-operated or hand-held instruments
4
V
IN
5
V
OUT
ON/OFF
3
THERMAL
PROTECT
2
RESET
1
7
GND
Cd
SL01528
Figure 1. Block diagram.
2001 Oct 03
2
853–2292 27197
Philips Semiconductors
Product data
300 mA LDO with ON/OFF control and
independent delayed RESET function
SA57026
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
SA57026
NAME
SOP-7B
DESCRIPTION
small outline 7-pin surface mount (see dimensional drawing)
TEMPERATURE
RANGE
–40 to +85
°C
NOTE:
The device has two reset threshold options.
XX
SA57026D
SA57026F
Output voltage (Typ.)
3.3 V
3.3 V
Reset threshold (Typ.)
4.20 V
3.90 V
Part number marking
Part number
SA57026DD
SA57026FD
Marking
ALU
ALV
PIN CONFIGURATION
PIN DESCRIPTION
PIN
SYMBOL
GND
RESET
Ground.
RESET signal output pin. The output remains
low while V
DET
is below the reset voltage
threshold, and for an extnerl set time delay
Cd pin after V
DET
rises above reset
threshold.
Output voltage on/off control pin. Connect to
V
IN
if not used.
ON/OFF = LOW: Voltage output (Pin 5) OFF
ON/OFF = HIGH: Voltage output (Pin 5) ON
Voltage supply input pin.
Regulated voltage output pin.
Ground pin and heat sink.
Reset delay time capacitor pin.
RESET pin output delay time can be set by
capacitance connected to the Cd pin.
t
PLH
= 100000 x C
t
PLH
: transmission delay time (s).
C: capacitor value (F).
DESCRIPTION
1
2
GND
RESET
ON/OFF
V
IN
1
2
7
Cd
SA57026
3
4
6
GND
5
V
OUT
3
ON/OFF
SL01529
Figure 2. Pin configuration.
4
5
6
7
V
IN
V
OUT
GND
Cd
MAXIMUM RATINGS
SYMBOL
V
IN
I
OUT
T
oper
T
stg
P
D
Supply voltage
Output current
Operating temperature
Storage temperature
Power dissipation (Note 1)
PARAMETER
MIN.
–0.3
0
–40
–40
–
MAX.
+10
400
+85
+125
800
UNIT
V
mA
°C
°C
mW
NOTE:
1. When mounted on a 25
×
40
×
1 mm glass epoxy board.
2001 Oct 03
3
Philips Semiconductors
Product data
300 mA LDO with ON/OFF control and
independent delayed RESET function
SA57026
ELECTRICAL CHARACTERISTICS
T
amb
= 25
°C;
V
ON/OFF
= 1.6 V, unless otherwise specified.
SYMBOL
I
ccq1
I
ccq2
I
ccq3
Regulator
V
OUT
Output voltage
V
IN
= 5 V; I
OUT
= 30 mA
SA57026D
SA57025F
V
IN
= 3.2 V; I
OUT
= 150 mA
V
IN
= 4.4 to 5.5 V; I
OUT
= 30 mA
V
IN
= 5 V; I
OUT
= 0 to 300 mA
T
j
= –20 to +85
°C;
V
IN
= 5 V
V
IN
= 5 V; f = 120 Hz; V
ripple
= 1 V
p–p
;
I
OUT
= 30 mA
V
IN
= 5 V; f = 20 to 80 kHz;
V
ripple
= 1 V
p–p
; I
OUT
= 30 mA
V
ON/OFF
= 1.6 V
3.25
3.25
–
–
–
–
–
–
–
1.6
–0.3
3.30
3.30
0.15
10
20
100
50
40
5
–
–
3.35
3.35
0.3
20
120
–
80
120
10
V
IN
+0.3
0.4
V
V
V
mV
mV
ppm/°C
dB
µV
rms
µA
V
V
PARAMETER
No-load input current 1
No-load input current 2
Input current (OFF)
CONDITIONS
V
IN
= 5 V; I
OUT
= 0 mA
V
IN
= 4 V; I
OUT
= 0 mA
V
IN
= 5 V; V
ON/OFF
= 0.4 V
MIN.
–
–
–
TYP.
3
4
250
MAX.
8
–
–
UNIT
mA
mA
µA
V
IO
V1
V2
∆V
OUT
/∆T
RR
V
n
I
ON
V
th(H)
V
th(L)
Reset
V
DET
Input/output differential voltage
Line regulation
Load regulation
V
OUT
Temperature coefficient
(Note 1)
Ripple rejection (Note 1)
Output noise voltage (Note 1)
ON/OFF terminal current
HIGH threshold voltage
LOW threshold voltage
Detection voltage
V
IN
= HIGH-to-LOW
SA57026D
SA57025F
T
j
= –20 to +85
°C
V
IN
= HIGH-to-LOW-to-HIGH
V
IN
= 3.9 V; R
L
= 4.7 kΩ
V
IN
= 5 V
V
IN
= 3.9 V; R
L
= 0
Ω
V
IN
= 3.9 V; R
L
= 0
Ω;
T
amb
= –20 to +80
°C
Cd = 0.0
µF
V
IN
= 4 V to 5 V; Cd = 0.1
µF
4.11
3.81
–
100
–
–
5
3
–
5
–
4.20
3.90
100
–
100
–
–
–
30
10
30
0.65
4.29
3.99
–
200
200
±0.1
–
–
90
20
90
0.85
V
V
ppm/°C
mV
mV
µA
mA
mA
µs
ms
µs
V
∆V
S
/∆T
∆V
S
V
OL
I
LO
I
OL1
I
OL2
t
PLH
t
PLH1
t
PHL
V
OPL
V
S
temperature coefficient (Note 1)
Hysteresis voltage
LOW-level output voltage
Output leakage current
LOW-level output current 1
LOW-level output current 2 (Note 1)
LOW-to-HIGH transmission delay
time (Note 1)
Reset delay time
HIGH-to-LOW transmission delay
time (Note 1)
Threshold operating voltage
V
OL
= 0.4 V
–
NOTE:
1. The parameter is guaranteed by design.
2001 Oct 03
4
Philips Semiconductors
Product data
300 mA LDO with ON/OFF control and
independent delayed RESET function
SA57026
APPLICATION INFORMATION
Input capacitor
An input capacitor of
≥1 µF
is required to eliminate the AC coupling
noise. This capacitor must be located as close as possible to V
IN
or
GND pin (not more than 1 cm) and returned to a clean analog
ground. Any good quality ceramic, tantalum or film capacitor will
work.
RESET output delay operation with an external capacitor from
Cd pin to GND
When the supply voltage crosses the release voltage (V
DET
) from a
low value to a value higher than the released voltage (V
DET
), the Cd
pin voltage starts to increase (charges up the external capacitor).
While the RESET output remains at LOW state condition until the
Cd pin voltage reaches the threshold operating voltage (V
OPL
) 0.4 V
typical; after that, the RESET output is reversed to HIGH state
condition.
The transmission delay time (t
PLH
) can be set with the capacitance
Cd of an external cpacitor as shown in Equation (1):
Output capacitor
Phase compensation is made for securing stable operation, even if
the load current varies. For this reason, an output capacitor with
good frequency characteristics is needed. Set it as close to the
circuit as possible, with wires as short as possible.
Tha value of the output capacitance has to be at least 47
µF
connected from V
OUT
to GND. When operating from sources other
than batteries, supply-noise rejection and transient response can be
improved by increasing the value of the input and output capacitors
and employing passive filtering techniques.
t
PLH
+
10
6
C
Eqn. (1)
(Time is expressed in seconds; capacitance in Farads.)
PCB layout
The component placement around the LDO should be done carefully
to achieve good dynamic line and load response. The input and
noise capacitors should be kept close to the LDO.
The rise in junction temperature depends on how efficiently the heat
is carried away from the junction to ambient. The junction to lead
thermal impedance is a characteristic of the package and fixed. The
thermal impedance between lead to ambient can be reduced by
increasing the copper area on the PCB. Increase the input, output
and ground trace area to reduce the junction-to-ambient impedance.
ON/OFF
The regulator is fully enabled when a logic HIGH is applied to this
input. The regulator enters shutdown when a logic LOW is appplied
to this input. During shutdown, regulator output voltage falls to zero,
RESET remains valid and supply current is reduced to 5
µA
(typ). If
the function is not to be used, the ON/OFF pin should be tied to V
IN
.
RESET output
The SA57066 has an Active-LOW RESET output. The RESET
output is driven Active-LOW within 30
µs
typical (when Cd is zero
capacitance). The time delay can be adjusted up to 10 ms typical
(when Cd is 0.1
µF)
of V
DET
falling through the reset voltage
threshold. RESET is maintained Active-HIGH after V
DET
rises above
thre reset threshold.
V
IN
4
C
1
µF
R
4.7 kΩ
2
RESET
3
1
6
5
V
OUT
SA57026
7
Cd
C
OUT
47
µF
R
C
0.1
µF
ON/OFF
SL01530
Figure 3. Typical application circuit.
2001 Oct 03
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
