PF617-04
SED1765
SED1765
LCD Driver
SSC5000Series
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Corresponding to Large Capacity MIM LCD Panel
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PWM Method Gradation Display
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Wide Range of LCD Driving Voltage
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160-output Driver
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DESCRIPTION
The SED1765 is an LCD driver for driving the segment side, gradations by the PWM (Pulse Width Modulation)
method. The SED1765 makes it possible to display gradations of dot matrix large MIM liquid crystal panel, and
is used with the SED1177 as common driver.
The adoption of the PWM method and control of pulse position have brought flicker-free high definition gradation
display. Also, this driver has 160 LCD output terminals of high driving voltage. For example, the SED1765 can
drive a gradation displaying liquid crystal panel of 640
×
480 dots with the SED1177 at 7 drivers.
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FEATURES
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Liquid crystal display in 16 gradations
• Gradation signal ..................................................... 4 bits x 2
• On-pulse positions can be set in 1H area, and pulse width modulations for centering and right justification can
be selected.
• Gamma compensation suitable for liquid crystal characteristics is easy.
• 4 gradations and 8 gradation can correspond to each other.
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Number of LCD driving output terminals160
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Operating frequency
• Max. 12 MHz (When the enable automatic transfer facility is used)
One screen driving method can apply to 640 x 480 dots.
• Max. 16 MHz (When the enable automatic transfer facility is not used)
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Range of liquid crystal driving voltage +14 to +40 V
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The inhibit function makes display blanking possible.
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Selectable output shift direction.
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The enable automatic transfer facility has realized cascade connection and power reduction. (Enable signals
need not be generated by controller.)
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The offset voltage of liquid crystal driving power supply can be adjusted for the V
DDH
and GND levels.
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Logic circle power supply .......................................... 5.0 V
±10%
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Package :
Die form .............................................. SED1765D
0A
(Al pad)
.............................................. SED1765D
0B
(Au bump)
TCP
.............................................. SED1765T
0A
(Outer lead pitch =0.18 mm)
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SED1765
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BLOCK DIAGRAM
V
DDH
V
CC
GND
O0
O159
V
2
V
3
V
0
V
5
FR
INH
GCP
RES
Gray scale
control
Decoder
Voltage
control
Level shifter, 160 bits
LCD driver, 160 bits
LP
D0-D3
D4-D7
SHL
EI01
EI02
XSCL
T
Enable control
Data
control
Latch B, 160 bits
Latch A, 160 bits
Two-way shift register
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PIN DESCRIPTION
Power
supply
V
0
to V
5
Number
of pins
160
Pin name
O0 - O159
I/O
O
Function
To output the liquid crystal driving segment (column).
The output changes at the LP fall edge.
To input 4-bit data for generating gradation.
D4, D0 : LSB
D7, D3 : MSB
To input clock signals.
The shift register operates at the fall edge.
To input display data latch signal.
Display data is latched at the fall edge.
Enable input and output.
Cascade connection is made to the next EIO.
Enable signal changes at the XSCL fall edge.
To input basic clock signal for generating gradation.
Basic clock signals operate at the fall edge.
D0 - D3
D4 - D7
I
GND to
V
CC
↑
↑
↑
8
(1)
XSCL
I
1
LP
I
1
EIO1 - 2
I/O
2
GCP
I
↑
1
2
SED1765
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PIN DESCRIPTION
(Cont)
Pin name
RES
I/O
I
Function
Power Number
supply of pins
1
To change PWM waveform rising/falling,
GND to
V
OFF
→
V
ON
, V
ON
→
V
OFF
and mode change-over signals. V
CC
Before RES signal input
V
OFF
(V
2
, V
3
)
→
V
ON
(V
0
, V
5
) Transition mode
After RES signal input
V
ON
(V
0
, V
5
)
→
V
OFF
(V
2
, V
3
) Transition mode
To input selection signals of shift register shift direction.
When D0 to D3 and D4 to D7 are corresponded to An and
Bn respectively, the relations between gradation data and
segment output are as per the following table:
(n means data sequence.)
O output
SHL
159 158 157
L
H
(Note)
A0
B0
A1
…
…
…
2
1
0
EIO1
EIO2
B78 A79 B79 Output Input
A1
B0
A0
Input Output
EIO
↑
SHL
I
1
B79 A79 B78
The relations between data and segment output are
set irrespectively of the number of shift clocks.
↑
—
—
—
1
1
1
5
FR
GND
V
CC
V
0
, V
2
, V
3
V
5
, V
DDH
INH
I
To input liquid crystal driving AC signal
Power supply Common power supply
Power supply Logic power supply
Power supply Power supply of liquid crystal driving bias
V
DDH
≥
V
0
> V
2
≥
7/9 V
DDH
, 2/9 V
DDH
≥
V
3
> V
5
≥
GND
I
To input inhibit signals
Inhibit signals are active on “L.” At the time all segment
outputs comes to be of non-selection level (V
2
and V
3
).
Test input. Usually “L” is available.
GND to
V
CC
↑
1
T
I
1
Number of NC terminals is shown in ( ). Total 186 pins
3
SED1765
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ABSOLUTE MAXIMUM RATINGS
GND = 0 V
Rating
Supply voltage (1)
Supply voltage (2)
Supply voltage (3)
Input voltage
Operating temperature
Storage temperature 1
Storage temperature 2
Symbol
V
CC
V
DDH
V
0
, V
2
, V
3
, V
5
V
I
Topr
Tstg 1
Tstg 2
Value
–0.3 to +7.0
–0.3 to +45.0
–0.3 to V
DDH
+0.3
–0.3 to V
CC
+0.3
–20 to +75
–65 to +150
–55 to +100
Unit
V
V
V
V
°C
°C
°C
Note 1 : Storage temperature (1) specifies those of solid chip.
Note 2 : Let the voltages of V
DDH
, V
0
, V
2
, V
3
and V
5
maintain the condition, V
DDH
≥
V
0
≥
V
2
≥
V
3
≥
V
5
≥
GND, all the time.
V
DDH
V
0
V
2
40V
Vcc
GND
5V
V
3
V
5
Note 3 : If the logic circuit power supply comes to float while voltage is applied to the
liquid crystal driving circuit, the LSI may be broken permanently. So, prevent
the logic circuit power supply from floating.
Pay special attention to the power supply sequence when the system is
switched on or off.
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SED1765
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ELECTRICAL CHARACTERISTICS
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DC Characteristics
(Unless otherwise designated, there shall be the following conditions:
GND = 0V, V
CC
= +5 V
±10%,
Ta = –20 to +75°C.)
Characteristic
Supply voltage (1)
Supply voltage (2)
Selection input voltage
Non-selection input
voltage (1)
Non-selection input
voltage (2)
“H” input voltage
“L” input voltage
“H” output voltage
“L” output voltage
Input leak current
Input-output leak current
Static current
V
IH
V
IL
V
OH
V
OL
I
LI
I
LI/O
I
GND
I
OH
= –0.4 mA
I
OL
= 0.4 mA
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
V
DDH
= 14.0 to 40.0 V
V
IH
= V
CC
, V
IL
= GND
Output resistance *1
R
0
V
ON
=
0.5 V
V
DDH
10.0 V
20.0 V
30.0 V
Current consumed (1)
I
CC
V
CC
= 5.0 V, V
IH
= V
CC
V
IL
= GND
f
XSCL
= 10.8 MHz,
f
LP
= 33.8 kHz,
f
GCP
= 0.54 MHz,
FR = 70 Hz
D0 to D7 = F0F0…,
No load
V
CC
= 5.0 V
V
5
= 0 V, V
3
= 4 V
V
2
= 26 V,
V
0
= V
DDH
= 30 V
Other conditions are
same with those of I
CC
.
Ta = 25°C, Freq = 1 MHz
Ta = 25°C, Freq = 1 MHz
2.0
1.5
1.3
2.5
6.5
3.5
3.0
5.0
mA
V
CC
kΩ
O 0 to 159
0.8×V
CC
GND
V
CC
–0.4
GND
V
3
, V
5
Symbol
V
CC
V
DDH
V
0
V
2
Condition
Min.
4.5
14.0
V
DDH
–2.5
7/9
×
Typ.
5.0
Max.
5.5
40.0
V
DDH
V
DDH
2/9
×
V
DDH
V
CC
0.2×V
CC
V
CC
0.4
2.0
5.0
25
Unit
V
V
V
V
Applicable pin
V
CC
V
DDH
V
0
V
2
V
0
≥
V
2
≥
V
3
≥
V
5
Recommendation value
V
DDH
GND
V
V
3
, V
5
V
V
V
V
µA
µA
µA
All input pins
EIO1, EIO2
Other than EIO
EIO1, 2
GND
Current consumed (2)
I
DDH
0.5
1.2
mA
V
DDH
Input terminal capacity *2
Input-output terminal *2
capacity
C
I
C
I/O
8.0
15.0
pF
pF
Other than EIO
EIO1, 2
* 1. To be specified within the ranges of the input voltages, V0, V2, V3 and V5.
* 2. Capacity of solid chip is shown.
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