SN54/74LS73A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These
dual flip-flops are designed so that when the clock goes HIGH, the inputs are
enabled and data will be accepted. The logic level of the J and K inputs may
be allowed to change when the clock pulse is HIGH and the bistable will per-
form according to the truth table as long as minimum set-up times are ob-
served. Input data is transferred to the outputs on the negative-going edge of
the clock pulse.
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM
(Each Flip-Flop)
J SUFFIX
CERAMIC
CASE 632-08
14
Q
13 (8)
Q
12 (9)
1
CLEAR
2 (6)
K
3 (10)
1 (15)
CLOCK (CP)
J
14 (7)
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
OUTPUTS
K
X
h
h
l
l
Q
L
q
L
H
q
Q
H
q
H
L
q
Ceramic
Plastic
SOIC
MODE SELECT — TRUTH TABLE
INPUTS
OPERATING MODE
CD
Reset (Clear)
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
H
H
H
H
J
X
h
l
h
l
LOGIC SYMBOL
14
1
3
J
CP
Q
12
7
5
J
CP
Q
9
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
l, h (q) =
prior to the HIGH to LOW clock transition.
K C Q
D
2
13
10
K C Q
D
6
8
VCC = PIN 4
GND = PIN 11
FAST AND LS TTL DATA
5-68
SN54/74LS73A
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
J, K
Clear
Clock
IIH
Input HIGH Current
J, K
Clear
Clock
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
J, K
Clear, Clock
– 20
0.1
0.3
0.4
– 0.4
– 0.8
–100
6.0
mA
VCC = MAX, VIN = 7.0 V
0.35
0.5
20
60
80
V
µA
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
IIL
IOS
ICC
mA
mA
mA
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
fMAX
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay,
Clock to Output
Min
30
Typ
45
15
15
20
20
Max
Unit
MHz
ns
Figure 1
ns
Test Conditions
Figure 1
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS
(TA = 25°C)
Limits
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width High
Clear Pulse Width
Setup Time
Hold Time
Min
20
25
20
0
Typ
Max
Unit
ns
ns
ns
Figure 1
ns
Test Conditions
Figure 1
Figure 2
VCC = 5.0 V
FAST AND LS TTL DATA
5-69
SN54/74LS73A
AC WAVEFORMS
J or K *
th(L) = 0
ts(L)
CP
1.3 V
tW(L)
1.3 V
tW(H)
tPHL
Q
1.3 V
tPLH
1.3 V
1
fMAX
1.3 V
th(H) = 0
1.3 V
ts(H)
tPLH
1.3 V
tPHL
Q
1.3 V
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays, Data
Set-Up and Hold Times, Clock Pulse Width
tW
SET
1.3 V
1.3 V
tW
CLEAR
tPLH
1.3 V
tPHL
Q
1.3 V
tPHL
1.3 V
tPLH
1.3 V
Q
1.3 V
1.3 V
Figure 2. Set and Clear to Output Delays,
Set and Clear Pulse Widths
FAST AND LS TTL DATA
5-70
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
