Standard ICs
ID ROM for CRT displays supporting
plug & play
BU9881 / BU9881F
The BU9881 / BU9881F is a 1k bit EEPROM conforming to the standardized interface that enables Plug & Play on
CRT displays.
•
Applicationsdisplays
Desktop CRT
Desktop LCD displays
Other desktop PC displays
External CRT displays for notebook computers
•
Features EEPROM with configuration of 128
1) 1kbit serial
words
×
8 bits.
2) Supports I
2
C bus.
3) Supports DDC1™/ DDC2™ interfaces for monitor
IDs.
∗
DDC is a registered trademark of VESA.
4) Supports clock frequencies of 100kHz and 400kHz.
5) Switching from DDC2 to DDC1 enabled using mode
pin.
•
Absolute maximum ratings (Ta = 25°C)
Parameter
Applied voltage
Power
dissipation
BU9881
BU9881F
Tstg
Topr
—
Symbol
V
CC
Pd
Limits
– 0.3 ~ + 6.5
500
∗
1
350
∗
2
– 65 ~ + 125
– 40 ~ + 85
– 0.3 ~ V
CC
+ 0.3
Unit
V
mW
°C
°C
V
Storage temperature
Operating temperature
Voltage for various pins
∗
1 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.
∗
2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C.
∗
If input exceeds the absolute maximum ratings, the device may break down.
•
Recommended operating conditions
Parameter
Power supply voltage
Input voltage
Symbol
V
CC
V
IN
Limits
2.7 ~ 5.5
0 ~ V
CC
Unit
V
V
1
Standard ICs
BU9881 / BU9881F
•
Block diagram
MODE
1
7bit
Address
decoder
Slave-word
address register
1,024 bit EEPROM Array
8
8bit
V
CC
N.C.
2
7bit
Data register
7
VCLK
START
N.C.
3
Control circuit
STOP
6
SCL
GND
4
High voltage generator
Power supply
voltage detection
ACK
5
SDA
•
Pin descriptions
Pin No.
1
2, 3
4
5
6
7
8
Pin name
MODE
N.C.
GND
SDA
SCL
VCLK
V
CC
I/O
I
—
—
I/O
I
I
—
Function
Transmit-only mode switching pin
(pulled down when used in open state)
Not connected
Reference voltage of 0V for all input / output
Slave and word address serial data input / output
Serial clock input pin for I
2
C mode
Clock input pin for transmit-only mode
Connect the power supply
The SDA pin is Nch open drain output, and should be used with an external pull-up resistor added.
2
Standard ICs
BU9881 / BU9881F
•
Electrical characteristics (unless otherwise noted, Ta = – 40 to + 85°C, Vcc = 2.7V to 5.5V)
Parameter
Input high level voltage 1
Input low level voltage 1
Input high level voltage 2
Input low level voltage 2
Input high level voltage 3
Input low level voltage 3
Output low level voltage
Input leakage current 1
Input leakage current 2
Output leakage current
Operating current consumption
Standby current
Symbol
V
IH1
V
IL1
V
IH2
V
IL2
V
IH3
V
IL3
V
OL
I
LI1
I
LI2
I
LO
I
CC
I
SB
Min.
0.7V
CC
—
2.0
—
—
0.8V
CC
—
—
–1
–1
–1
—
—
Max.
—
0.3V
CC
—
0.8
0.4
—
0.4
0.4
1
15
1
3
30
Unit
V
V
V
V
V
V
V
µA
µA
µA
mA
µA
Conditions
(SCL, SDA)
(SCL, SDA)
(VCLK)
V
CC
= 4.5 ~ 5.5V (VCLK)
V
CC
= 2.7 ~ 4.5V (VCLK)
(MODE)
(MODE)
I
OL
= 3.0mA(SDA)
V
IN
= 0V ~ V
CC
(SCL · SDA · VCLK)
V
IN
= 0V ~ V
CC
(MODE)
V
OUT
= 0V ~ V
CC
(SDA)
V
CC
= 5.5V, tWR = 10ms
V
CC
= 5.5V, MODE = GND
VCLK · SDA · SCL = V
CC
Measurement
Circuit
—
—
—
—
—
—
Fig.1
Fig.2
Fig.2
Fig.2
Fig.3
Fig.4
•
Measurement circuits
V
CC
V
CC
V
CC
3.0mA
I
LO
I
LI
V
CC
MODE, VCLK
SDA, SCL
SDA
A
V
V
OL
V
OUT
= 0 ~ V
CC
V
IN
= 0 ~ V
CC
GND
GND
Data set when output is LOW
Fig. 1 LOW output voltage measurement circuit
V
CC
Fig. 2 Input / output leakage current measurement circuit
V
CC
A
V
CC
I
CC
V
CC
A
V
CC
ISB
100 / 400 kHz clock
Write / read input
SCL, VCLK
SCL
SDA
VCLK
MODE
SDA
MODE
V
CC
GND
GND
Fig. 3 Current consumption measurement circuit
Fig. 4 Standby current measurement circuit
3
Standard ICs
BU9881 / BU9881F
•
Operation timing characteristics (unless otherwise noted, Ta = – 40 to + 85°C)
Parameter
Clock frequency
Data clock HIGH time
Data clock LOW time
SDA / SCL rise time
SDA / SCL fall time
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus release time prior to start of transfer
Internal write cycle time
Effective noise elimination interval (SCL, SDA pins)
Symbol
f SCL
t HIGH
t LOW
tR
tF
t HD: STA
t SU: STA
t HD: DAT
t SU: DAT
t PD
t DH
t SU: STO
t BUF
t WR
tI
Standard Mode
V
CC
= 2.7 ~ 5.5V
Min.
0
4.0
4.7
—
—
4.0
4.7
0
250
0
0
4.7
4.7
—
—
Max.
100
—
—
1.0
1.0
—
—
—
—
3.5
—
—
—
10
—
High-speed Mode
V
CC
= 4.5 ~ 5.5V
Min.
0
0.6
1.3
—
—
0.6
0.6
0
100
0
0
0.6
1.3
—
—
Max.
400
—
—
0.3
0.3
—
—
—
—
0.9
—
—
—
10
50
kHz
µs
µs
µs
µs
µs
µs
ns
µs
µs
µs
µs
µs
ms
ns
Unit
•
Transmit – only MODE
Parameter
VCLK output delay time
VCLK HIGH time
VCLK LOW time
Mode transition time
Power up time for transmission
Symbol
TVAA
TVHIGH
TVLOW
TVHZ
TVPU
Standard Mode
V
CC
= 2.7 ~ 5.5V
Min.
—
4.0
4.7
—
0
Max.
500
—
—
500
—
High-speed Mode
V
CC
= 4.5 ~ 5.5V
Min.
—
0.6
1.3
—
0
Max.
500
—
—
500
—
ns
µs
µs
ns
ns
Unit
4
Standard ICs
BU9881 / BU9881F
•
Circuit operation
Basic operation
The BU9881 / BU9881F is equipped with two modes, a normal I
2
C bus mode (bi-directional mode) and a transmit-
only mode.
• The transmit-only mode can be accessed by turning on the power supply to the IC, or by using the software to
control the mode. In this mode, operation is synchronized to the clock input to VCLK, and it is possible to read
the contents of the EEPROM memory from the SDA pin.
• To switch from the transmit-only mode to the I
2
C bus mode, the clock signal that recognizes the switching of
HIGH to LOW is input to the SCL pin. The I
2
C bus mode is effective following the edge of that clock.
• To switch from the I
2
C bus mode to the transmit-only mode, the software can be used to control the mode, or
the power supply to the IC can be turned off and then on again. This switches back to the transmit-only mode.
(1) Description of mode pin functions
As shown in the illustration below, the software can be used to control the mode pin, enabling switching from the
I
2
C bus mode to the transmit-only mode.
Set HIGH for 2µs or longer
Set LOW for 2µs or longer
MODE
SCL
I
2
C MODE
TRANSMIT ONLY MODE
I
2
C MODE
Fig. 5
1)Transmit-only mode
• This command causes all of the data written to the EEPROM to be read. After the transmit-only mode is
entered, inputting the VCLK clock causes the data to be read from the SDA pin.
• The SDA pin is in the "Hi-Z" state for the first nine clock signals input, and data is output sequentially, timed to
the rise of the clock starting with the tenth clock.
• Addresses are incremented automatically as clock pulses continue to be input to VCLK, with the data from the
next address being read in sequence. While this is being done, the null bit (HIGH data) is output between the
data of one address and that of the next address.
• When the power supply is turned on, and when the mode is switched from the I
2
C bus mode to the transmit-only
mode, the output data for the transmit-only mode is synchronized to VCLK as follows:
Last address data→0h address data→1h address data→→→
and is incremented in sequence.
(Following the last address, processing shifts to the 0h address.)
Note: Reading in the transmit-only mode should not be done until the power supply has stabilized. When switch-
ing from the transmit-only mode to the I
2
C bus mode, assure the TVHZ time before beginning communica-
tions.
5
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